HKMG Gate Hard Mask Equalization Across PMOS and NMOS
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Solution Overview
Problem
In the fabrication of high-k metal gate transistors, the growth of epitaxial layers on PMOS regions often results in hard masks of different thicknesses compared to NMOS regions, affecting device performance.
Innovation Solution
A method is employed where a substrate with both PMOS and NMOS transistor regions is provided, and gate structures with different hard masks are formed. A patterned mask is used to selectively remove parts of the hard mask on the NMOS region, ensuring the thickness of the hard mask on both regions is equalized.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial layer growth is performed on PMOS region, then PMOS device performance is improved, but hard mask thickness becomes non-uniform between PMOS and NMOS regions
Solution Approach 1:
The patent divides the hard mask removal process into two segments: a first etching process that removes hard mask from both PMOS and NMOS regions, and a second etching process that selectively removes additional hard mask only from the NMOS region. This segmentation allows differential thickness adjustment to compensate for the non-uniformity introduced by epitaxial growth on the PMOS region.
Solution Approach 2:
The patent applies local quality by performing selective etching on the NMOS region to remove a greater amount of hard mask compared to the PMOS region. The patterned mask is strategically positioned to cover the PMOS region while exposing the NMOS region, enabling localized material removal to achieve uniform final hard mask thickness across both transistor types.
2Manufacturing precision
If selective hard mask removal is performed on NMOS region, then hard mask thickness uniformity is improved, but process complexity increases
Solution Approach 1:
The patent employs preliminary action by forming a patterned mask before the selective etching process. This pre-formed mask structure defines the NMOS region boundaries in advance, enabling the subsequent selective removal of hard mask from only the NMOS region. The patterned mask is created through standard photolithography techniques, making the complex selective removal process manageable and reproducible.
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first transistor region and a second transistor region and then forming a first gate structure on the first transistor region and a second gate structure on the second transistor region, in which the first gate structure includes a first hard mask, the second gate structure includes a second hard mask, and the first hard mask and the second hard mask have different thicknesses. Next, a patterned mask is formed around the first gate structure and the second gate structure, and then part of the first hard mask is removed.