High-k Metal Gate Isolation Structure for FinFET Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming high-k metal gates in semiconductor devices face challenges such as reduced end-cap processing windows and potential damage to interlayer dielectric layers, along with undesired shifts in threshold voltage during the cutting process.
Innovation Solution
A method involving the formation of a high-k dielectric layer and capping layer before cutting, followed by the creation of an isolation feature and a conductive electrode, which reduces material layers on isolation feature sidewalls and completes the cutting process before forming the conductive gate electrode, minimizing adverse effects from etchant gases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the cutting process is performed before forming the conductive gate electrode, then the end-cap processing window is enlarged and adverse effects on interlayer dielectric are reduced, but the threshold voltage may shift during the cutting process
Solution Approach 1:
The patent applies preliminary action by forming the high-k dielectric layer and capping layer before performing the cutting process. This sequence allows the cutting to be done when the structure is more stable, enlarging the end-cap processing window while minimizing damage to interlayer dielectric layers. The threshold voltage shift is managed by completing critical formation steps before exposure to etchant gases.
Solution Approach 2:
The patent segments the gate formation process into distinct stages: forming the high-k dielectric layer, forming the capping layer, performing the cutting process, and then forming the conductive gate electrode. This segmentation allows each step to be optimized independently, resolving the contradiction between processing window and threshold voltage stability.
2Reliability
If multiple material layers are formed along sidewalls of isolation features, then the isolation is more complete, but the end-cap processing window is reduced
Solution Approach 1:
The patent extracts the capping layer formation step and positions it before the cutting process, rather than forming multiple material layers along the sidewalls after cutting. This extraction reduces the number of material layers that would otherwise constrain the end-cap processing window, while still achieving complete isolation through the high-k dielectric layer and strategic capping layer placement.
3Manufacturing precision
If the cutting process is performed after forming the conductive gate electrode, then the gate structure is more complete, but damage to interlayer dielectric layers may occur
Solution Approach 1:
The patent performs the cutting action preliminarily, before forming the conductive gate electrode and interlayer dielectric layers. This preliminary cutting avoids subsequent damage to these sensitive structures that would occur if cutting were performed after their formation. The high-k dielectric layer and capping layer are already in place to protect the underlying structures during the cutting process.
Data Source
AI summary
A method of forming high-k metal gates (HKMGs) includes removing a dummy gate structure formed over a first fin and a second fin to form a trench that exposes portions of the first fin and the second fin, forming a high-k dielectric layer over the exposed portions of the first fin and the second fin, forming a capping layer over the high-k dielectric layer, forming a hard mask layer over the capping layer, such that the hard mask layer fills the trench completely, forming an isolation feature in the hard mask layer between the first fin and the second fin, the isolation feature having sidewalls that extend through the capping layer, removing the hard mask layer to expose the capping layer and the sidewalls of the isolation feature, and forming a conductive electrode over the capping layer and along the sidewalls of the isolation feature.