HKMG Integration for NVM Logic Memory Leakage
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Solution Overview
Problem
In emerging technology nodes, integrating logic and memory devices on a single semiconductor chip poses challenges due to inter-chip communication delays and high processing costs, necessitating innovative solutions for high-performance embedded memory that can reduce gate leakage and power consumption while enabling further scaling.
Innovation Solution
The integration of high-k metal gate (HKMG) technology in both memory and logic regions of an integrated circuit, where metal gate electrodes with high-k gate dielectrics are used to reduce gate leakage and power consumption, and simplify manufacturing processes by sharing fabrication steps, allowing for improved device performance and further scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional separate-chip memory and logic integration is used, then manufacturing cost is reduced, but inter-chip communication delay increases and performance is limited
Solution Approach 1:
The patent merges memory and logic devices into a single integrated circuit chip, eliminating the need for inter-chip communication. The memory device and logic device share the same substrate and fabrication process, enabling direct integration and removing communication delays between separate chips.
Solution Approach 2:
The integrated circuit employs a universal high-k metal gate structure that serves both the memory device and logic device. The same gate dielectric layer and metal gate electrode materials are used across different device types, simplifying manufacturing while enabling both memory and logic functions on one chip.
2Loss of energy
If conventional memory structures are used, then manufacturing process is simpler, but gate leakage and power consumption are high
Solution Approach 1:
The patent changes the gate dielectric parameter from traditional silicon dioxide to high-k dielectric materials, increasing the dielectric constant. This parameter change enables thinner effective oxide equivalent thickness while maintaining physical thickness, thereby reducing gate leakage and power consumption without requiring fundamentally new manufacturing processes.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric layers combined with metal gate electrodes. This composite approach creates a hybrid structure that leverages the high dielectric constant of the insulator and the conductive properties of the metal gate, achieving low leakage and low power consumption while remaining compatible with existing CMOS fabrication.
3Speed
If device scaling is pursued to improve performance, then speed increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent segments the gate structure into distinct functional layers: a high-k dielectric layer for electrical isolation and capacitance, and a metal gate layer for control. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall device performance and scalability.
Solution Approach 2:
The patent applies local quality by using different materials and structures in different regions of the device. The high-k metal gate structure is applied specifically to the memory and logic devices on the integrated circuit, while other portions of the chip can use traditional structures. This localized approach enables performance optimization in critical areas without requiring complete redesign of the entire manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate leakage and power consumption, enhances device speed, and improves reliability by integrating HKMG structures in both logic and memory regions, enabling efficient and cost-effective integration of logic and memory on a single chip.
Implementation Method 1
a first metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer
Implementation Method 2
metal gate electrodes with high-k gate dielectrics are used to reduce gate leakage and power consumption
Data Source
AI summary
The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control gate electrodes separated from a substrate by corresponding floating gates. A pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes. A logic region is disposed adjacent to the memory region and has a logic device with a metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer. The select gate electrodes or the control gate electrodes comprise metal and have bottom and sidewall surfaces covered by the high-k gate dielectric layer.