HKMG Gate Structure With Pillars for Multiple-Vt Planarization
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Solution Overview
Problem
As semiconductor technology advances, achieving multiple threshold voltage (Vt) capabilities in high-k metal gate (HKMG) processes becomes challenging due to reduced gate lengths, particularly in forming devices with different voltage requirements, such as memory and core circuits, where power supply voltages are reduced and gate leakage is a concern.
Innovation Solution
A method for forming a semiconductor structure with multiple-Vt design using dielectric layers of different thicknesses and dielectric or semiconductor pillars in the metal gate structure, where a thicker dielectric layer is used for high voltage devices and a thinner layer for low voltage devices, helping to mitigate dishing issues during planarization in the HKMG process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-k metal gate (HKMG) approach is used to reduce gate leakage and maintain performance, then device performance is improved, but the manufacturing process becomes complicated and introduces many issues
Solution Approach 1:
The patent divides the gate structure into multiple functional layers: a first dielectric layer for electrical isolation, a second dielectric layer for mechanical support, and a metal gate layer for electrical control. This segmentation allows each layer to be optimized independently, improving device performance while managing manufacturing complexity through modular fabrication processes
Solution Approach 2:
The patent applies different dielectric materials with different properties to different regions and layers of the gate structure. The first dielectric layer uses materials optimized for electrical isolation properties, while the second dielectric layer uses materials optimized for mechanical support and stress control, allowing local optimization of each layer's properties to achieve overall performance improvement without uniform complexity
2Adaptability or versatility
If dielectric layers of different thicknesses are used to provide multiple-Vt capability, then devices with different voltage requirements can be fabricated, but dishing issues occur during planarization
Solution Approach 1:
The patent implements different dielectric layer thicknesses in different regions: a first dielectric layer with greater thickness in first regions and a second dielectric layer with lesser thickness in second regions. This local variation in thickness allows multiple threshold voltage capabilities while the patent simultaneously addresses dishing issues by carefully controlling the deposition and planarization processes to maintain surface uniformity
Solution Approach 2:
The patent uses composite dielectric structures combining different materials (such as silicon oxide, silicon nitride, and silicon oxynitride) with different thicknesses in different regions. This composite approach enables multiple-Vt capability through varied thickness profiles while the material composition is selected to minimize dishing during planarization by balancing mechanical properties across the structure
3Productivity
If gate length is reduced to improve production efficiency and reduce costs, then productivity increases, but gate leakage increases and performance deteriorates
Solution Approach 1:
The patent employs a composite gate structure combining a high-k dielectric layer with a metal gate layer. The high-k dielectric material (such as hafnium oxide, zirconium oxide, or tantalum oxide) provides superior electrical isolation properties that compensate for the reduced gate length, while the metal gate layer provides excellent electrical control. This composite structure maintains device performance despite reduced dimensions, enabling continued scaling for improved productivity
Solution Approach 2:
The patent changes the dielectric constant parameter by transitioning from traditional silicon oxide (k≈3.9) to high-k materials (k>25). This parameter change allows the gate dielectric to provide sufficient electrical isolation and control even when the gate length is reduced, thereby maintaining device performance while enabling smaller feature sizes for improved production efficiency and reduced costs
Data Source
AI summary
A semiconductor structure includes a first device, a second device, and a plurality of pillars. The first device includes a first dielectric layer, a first high-k dielectric layer over the first dielectric layer, and a first metal gate structure. The second device includes a second dielectric layer, a second high-k dielectric layer over the second dielectric layer, and a second metal gate structure. The first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the second thickness is less than the first thickness. The pillars are disposed in the first metal gate structure. The pillars are separated from each other by the first metal gate structure.