HKMG Transistor STI Topography Protection Layer
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Solution Overview
Problem
The integration of flash memory cells in high-k/metal gate (HKMG) technology for field effect transistors (FETs) is challenging due to uneven shallow trench isolation (STI) topography, which affects the reliability and operational characteristics of semiconductor devices, as conventional processing methods lead to residual HKMG material outside the gate electrode stack that cannot be properly encapsulated.
Innovation Solution
A method is introduced to form a semiconductor device with integrated memory cells within the HKMG technology by creating a protection layer over the STI region, allowing for decoupled etching and cleaning processes that maintain a smooth STI topology, enabling the formation of a field effect transistor (FET) with a high-k dielectric layer and metal gate structure without affecting the logic area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional processing methods are used for integrating flash memory cells in HKMG technology, then the manufacturing process can be completed, but residual HKMG material remains outside the gate electrode stack causing uneven STI topography and reliability issues
Solution Approach 1:
A protection layer is formed over the STI region before the etching and cleaning processes that remove residual HKMG material. This preliminary protective action prevents damage to the STI topography while allowing subsequent selective removal of residual material, thereby maintaining both manufacturing precision and device reliability
Solution Approach 2:
The protection layer acts as an intermediary element between the etching/cleaning processes and the STI region. It selectively protects the STI area from harmful process effects while allowing the necessary removal of residual HKMG material, resolving the contradiction between achieving clean fabrication and maintaining topography uniformity
2Manufacturing precision
If etching and cleaning processes are performed to remove residual HKMG material, then manufacturing precision improves, but the high-k gate dielectric becomes damaged
Solution Approach 1:
The protection layer serves as an intermediary barrier that allows etching and cleaning processes to selectively remove residual HKMG material while preventing these same processes from damaging the high-k gate dielectric. This intermediary structure enables precise material removal without compromising dielectric integrity
Solution Approach 2:
The protection layer provides localized protection specifically to the STI region where residual material removal is needed, while leaving the gate dielectric area exposed for proper processing. This local differentiation allows selective removal of harmful residues without affecting the integrity of the gate dielectric structure
3Ease of manufacture
If the STI region is exposed during memory cell formation, then manufacturing flexibility is maintained, but the STI topology becomes uneven affecting subsequent FET formation
Solution Approach 1:
The protection layer is formed preliminarily over the STI region before memory cell formation processes begin. This preliminary protection maintains STI topology smoothness throughout subsequent processing steps, ensuring that FET formation can proceed with proper alignment and spacing without being affected by uneven STI surfaces
Solution Approach 2:
The protection layer serves multiple functions: it protects the STI region from topography degradation, allows flexible processing of memory cells, and can be selectively removed later. This multi-functionality resolves the contradiction between maintaining manufacturing flexibility and preserving STI topology smoothness
Data Source
AI summary
A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.