High-K Metal Gate Transistor Fabrication via Sacrificial Layer Segmentation
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Solution Overview
Problem
The difference in work function materials between PMOS and NMOS transistors in CMOS devices affects performance stability and yield, particularly in SRAM devices, due to difficulties in filling and removing gate electrode layers and potential material diffusion, leading to mismatches and performance deterioration.
Innovation Solution
A method for fabricating high-K metal gate transistors involves forming sacrificial layers and work function layers in specific openings to avoid material diffusion and mismatch issues, with a sacrificial layer filling the first opening to facilitate the formation of the second work function layer and gate electrode layer in the second opening, and removing the sacrificial layer to form the first work function layer and gate electrode layer in the first opening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different work function materials are used for PMOS and NMOS transistors, then the work function requirements for each transistor type are met, but performance stability and yield deteriorate due to material diffusion and interface bonding issues
Solution Approach 1:
The transistor structure is segmented into distinct regions (first region and second region) with separate openings, allowing different work function materials to be deposited in isolated areas. This segmentation prevents material diffusion between regions while maintaining the specific work function requirements for each transistor type, thereby improving performance stability without excessive fabrication complexity.
Solution Approach 2:
Different work function materials are applied to different local regions (PMOS region with first work function material, NMOS region with second work function material) based on their specific electrical requirements. This local quality approach ensures each region has the optimal material properties for its function while the overall structure maintains consistency and controllability.
2Manufacturing precision
If gate electrode layers are formed in deep openings, then the gate structure is completed, but void formation and interface bonding issues occur reducing manufacturing precision
Solution Approach 1:
A sacrificial layer is deposited in the first opening before forming the gate electrode layer. This preliminary action provides a foundation that facilitates complete filling of the gate electrode material and ensures good interface bonding between the gate electrode and underlying structures, preventing void formation in deep openings while maintaining reasonable process complexity.
Solution Approach 2:
The sacrificial layer acts as an intermediary between the substrate and the gate electrode layer. It mediates the interface bonding process, ensuring proper adhesion and preventing voids during the filling of deep openings. After serving its purpose, the sacrificial layer is removed, leaving a high-quality interface without adding permanent structural complexity.
3Productivity
If work function layers are formed simultaneously in both regions, then fabrication efficiency is maintained, but material diffusion causes mismatch and performance deterioration
Solution Approach 1:
The fabrication process is segmented into sequential steps for different regions. The sacrificial layer in the first region prevents simultaneous work function material deposition in both regions, thereby controlling material distribution and preventing diffusion-related mismatches while maintaining overall fabrication efficiency through structured process flow.
4Reliability
If the gate structure is formed with deep openings, then the transistor geometry is achieved, but residual contaminations remain affecting yield
Solution Approach 1:
The sacrificial layer is deposited in advance in the first opening, creating a structured foundation that facilitates complete and clean filling of the gate electrode layer. This preliminary action ensures that no voids or residual contaminations are trapped during the filling process, improving yield while maintaining reasonable manufacturing ease through a systematic approach.
Data Source
AI summary
The present disclosure provides HKMG transistor structures and fabrication methods thereof. An exemplary method includes providing a base substrate having a first region and a second region; forming a dielectric layer having a first opening in the first region and a second opening in the second region over; forming a gate dielectric layer on a side surface of the first opening and a portion of the base substrate in the first opening and on a side surface of the second opening and a portion of the base substrate in the second opening; filling a sacrificial layer in the first opening; forming a second work function layer in the second opening and a second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming a first work function layer in the first opening and a first gate electrode layer on the first work function layer.