High-Level Language to HDL Translation via API Segmentation
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Solution Overview
Problem
Current methods struggle to translate all high-level language syntaxes and semantics into HDL codes, particularly failing to support complete translation of software language syntaxes like pointers and two-dimensional arrays, limiting their application in digital circuit design.
Innovation Solution
A method involving marking API in high-level language codes, separating them into software and hardware parts, compiling the software part with a main compiler like GCC, and translating the hardware part into HDL code using a translator, which is then executed in cooperation with a main core and dedicated hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional translation tools or methods are used to translate high-level language codes into HDL codes, then translation capability is limited to system level languages or portions of high-level language syntaxes, but the ability to support complete high-level language syntaxes and semantics is insufficient
Solution Approach 1:
The patent segments the translation process into distinct modules: a front end for lexical and syntactic analysis, a middle end for semantic analysis and optimization, and a back end for code generation. This segmentation allows each module to handle specific aspects of high-level language translation independently, enabling support for complete syntaxes and semantics while managing system complexity through modular architecture.
Solution Approach 2:
The patent introduces an intermediate representation (IR) as a mediator between the front end and back end. The IR serves as a language-independent data structure that captures the semantic meaning of high-level code, allowing the translation system to handle diverse high-level languages and HDL targets without increasing overall complexity. This intermediary enables complete syntax support while maintaining manageable system structure.
2Productivity
If high-level language codes are translated into HDL codes using existing methods, then translation speed and efficiency are limited, but productivity in digital circuit design is reduced
Solution Approach 1:
The patent performs preliminary semantic analysis and optimization in the middle end before code generation. By analyzing semantics and applying optimizations early in the translation process, the system reduces the complexity of the back end code generation task, thereby improving overall translation efficiency and reducing total translation time.
Solution Approach 2:
The patent implements a continuous translation pipeline where the front end, middle end, and back end operate in sequence without interruptions. The intermediate representation allows seamless data flow between stages, eliminating re-processing and maintaining continuous useful action throughout the translation process, thus improving productivity and reducing translation time.
3Reliability
If complete high-level language syntaxes are supported in translation, then translation accuracy and completeness are improved, but the complexity of the translation tool increases
Solution Approach 1:
The patent divides the translator into specialized components: lexical analyzers for syntax recognition, semantic analyzers for meaning interpretation, and code generators for HDL output. Each component handles specific aspects of language translation, enabling complete syntax support while keeping individual component complexity manageable through clear separation of concerns.
Solution Approach 2:
The intermediate representation serves as a standardized mediator that captures complete semantic information from high-level languages in a language-independent format. This IR structure enables the translator to support complete syntaxes and semantics reliably while managing complexity by providing a uniform interface between analysis and generation stages.
4Ease of operation
If high-level language codes are directly translated into HDL codes without separation, then development simplicity is maintained, but the ability to optimize and verify hardware-software partitions is reduced
Solution Approach 1:
The patent automatically segments high-level language code into hardware and software parts during translation. The front end identifies hardware-eligible constructs, the middle end analyzes their semantic meaning, and the back end generates appropriate HDL code for hardware parts while keeping software parts in compilable form. This segmentation maintains development simplicity while enabling optimization and verification of hardware-software partitions.
Solution Approach 2:
The translation system performs self-service by automatically analyzing the input code and determining which parts are suitable for hardware implementation. The semantic analyzer identifies hardware-eligible operations and the code generator automatically partitions the code, eliminating the need for manual hardware-software separation while maintaining development simplicity and enabling optimization.
Data Source
AI summary
The present invention is directed to a method and system for translating a high programming level language code such as C, C++, Fortran, Java or the like into a HDL code such as Verilog or VHDL. The system includes: a C-to-C source translator which reads user API from a translation-targeted high level language code marked with the user API, separates the translation-targeted high level language code into a hardware code part and a software code part, and stores the hardware code part and the software code part in separate files; a main compiler which compiles the stored software code part; a translator which translates the stored hardware code part into a HDL code including one or more block modules and one top module; a main core which executes the compiled software code part; and a dedicated hardware which executes the HDL code.