HLAT With Read-Only Extended Page Tables for Memory Integrity

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Solution Overview

Problem

Virtual memory systems are susceptible to advanced kernel mode exploits that manipulate page tables, leading to incorrect physical page translations and potential corruption of memory pages, compromising memory integrity and confidentiality.

Innovation Solution

Implement hypervisor-managed linear address translation (HLAT) combined with multi-key memory encryption and integrity protection, using extended page tables (EPTs) to ensure read-only permissions for critical memory pages and enforce integrity checks, preventing unauthorized modifications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional page tables are used for address translation, then memory access speed is maintained, but the system becomes susceptible to kernel mode exploits that can manipulate page tables and corrupt memory

Engineering Contradiction:

Improvememory integrityVSAvoidaddress translation mechanism

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary layer (hypervisor-managed extended page tables) between the guest OS and physical memory. This intermediary protects against direct manipulation of page tables by kernel exploits while maintaining address translation functionality. The extended page tables act as a mediator that validates and controls the mapping between guest virtual addresses and host physical addresses.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The address translation mechanism is segmented into multiple hierarchical layers: guest virtual addresses are first translated to guest physical addresses via guest page tables, then to host physical addresses via hypervisor-managed extended page tables. This segmentation isolates the vulnerability of traditional page tables while preserving their translation function through additional protective layers.

Inventive Principle:

Principle #1Segmentation

2Ease of operation

If read-write permissions are granted to page tables for normal operation, then memory modification is enabled, but unauthorized modifications through exploits become possible

Engineering Contradiction:

Improvememory accessibilityVSAvoidunauthorized memory modification

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

Different permission levels are applied to different components of the address translation system. Guest page tables maintain read-write permissions for legitimate OS operations, while the hypervisor-managed extended page tables enforce read-only protection for critical structures. This local differentiation of permissions allows normal operation while preventing exploitation.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The system preemptively applies protective measures by having the hypervisor establish read-only permissions on extended page tables before guest OS operations can exploit them. This preliminary anti-action prevents kernel mode exploits from manipulating page table permissions, as the protective structure is already in place with appropriate access controls.

Inventive Principle:

Principle #9Preliminary anti-action

3Adaptability or versatility

If physical addresses are exposed to guest OS for address translation, then translation flexibility is maintained, but direct physical address manipulation and corruption risks increase

Engineering Contradiction:

Improveaddress translation flexibilityVSAvoidphysical memory protection

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent adds an additional dimension to address translation by introducing a second translation layer. Instead of directly exposing host physical addresses to the guest OS, the system translates guest virtual addresses to guest physical addresses, then separately translates guest physical addresses to host physical addresses through extended page tables. This dimensional addition protects physical memory while preserving translation flexibility.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The hypervisor-managed extended page tables serve as an intermediary that controls and validates the exposure of physical addresses to the guest OS. This intermediary structure allows address translation flexibility while preventing direct manipulation of host physical memory, as all address mappings must pass through the protected intermediate layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12455757B2Hypervisor-managed linear address translation and memory integrity

Publication Date: 2025.10.28 INTEL CORP

AI summary

An apparatus provides a processor configured to execute instructions of a hypervisor to provide hypervisor-managed linear address translation (HLAT) with integrity protection. The processor is to execute the instructions to select a first key identifier for a first virtual machine to run on the hypervisor, invoke a first platform configuration instruction to configure the first key identifier in the processor including generating an encryption key for the first key identifier and setting an integrity mode for the first key identifier, instantiate the first virtual machine including a first guest kernel, the first guest kernel to allocate a plurality of HLAT paging structures to be used to translate a guest virtual address to a guest physical address of a first memory page allocated for the first virtual machine, mark the plurality of HLAT paging structures with read-only permission, and assign the first key identifier to the first memory page.