High-Level Language Compilation for Programmable ICs
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Solution Overview
Problem
Current digital hardware design using hardware description languages (HDLs) like Verilog and VHDL lacks high-level abstractions to manage complexity, making it difficult to efficiently implement modern designs, whereas high-level languages (HLLs) like Java and C++ provide robust constructs for complexity management but require additional steps for hardware synthesis.
Innovation Solution
A method for compiling HLL programs that generates netlists and interface code for programmable circuitry within programmable ICs, allowing designers to implement functions without writing HDL code, using a command-line interface and tools like Vivado HLS synthesis tool to create executable programs and configuration data streams for hardware acceleration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If hardware description languages (HDLs) are used to describe digital hardware, then hardware circuits can be described with special constructs for registers and clocks, but the languages provide little in the way of high-level abstractions to manage the complexity of modern designs
Solution Approach 1:
The patent introduces a compilation system that acts as an intermediary between high-level programming languages and hardware description languages. This compiler translates HLL code into equivalent hardware descriptions, allowing designers to write code in familiar high-level languages while automatically generating the necessary hardware circuit descriptions, thus managing complexity without sacrificing hardware implementation capability
Solution Approach 2:
The patent replaces the manual process of writing hardware description language code with an automated compilation process. Instead of designers manually constructing hardware descriptions using HDL constructs, the system automatically synthesizes hardware circuit descriptions from high-level language code, eliminating the need for designers to directly work with complex hardware description syntax
2Productivity
If high-level languages are used to describe circuits, then designers can focus on algorithms rather than implementation details, but additional steps for hardware synthesis are required
Solution Approach 1:
The patent merges the high-level language compilation process with the hardware synthesis process into a unified system. The compilation system simultaneously performs language translation and hardware synthesis, generating both the executable code and the hardware circuit descriptions in one integrated process, thereby maintaining productivity benefits while reducing the apparent complexity through unification
Solution Approach 2:
The patent performs preliminary analysis and transformation of high-level language code to identify hardware-acceleratable functions before generating the final hardware descriptions. This preliminary processing stage prepares the code by marking functions for hardware implementation and generating appropriate interface code, thereby simplifying the subsequent synthesis steps and making the overall process more manageable
3Power
If functions are implemented on programmable circuitry, then hardware acceleration is achieved, but interface code generation and netlist creation are required
Solution Approach 1:
The patent implements a self-service mechanism where the compilation system automatically generates the necessary interface code and netlists without requiring manual intervention. The system analyzes the high-level language code, automatically creates interface functions for hardware communication, and generates the corresponding netlist representations, allowing hardware acceleration to be achieved while the system handles the complexity of interface generation autonomously
Data Source
AI summary
A method is provided for compiling an HLL program. A command is input that indicates a set of HLL source files to be compiled and a set of functions in the HLL source files that are to be implemented on programmable circuitry of a programmable IC. For a source file including one of the set of functions, a respective netlist is generated from HLL code of each of the set of functions included therein. Interface code is also generated for communication with the netlist. HLL code of the set of functions in the HLL source file is replaced with the generated interface code. Each HLL source file is compiled to produce a respective object file. The object files are linked to generate a program executable on the programmable IC. A configuration data stream is generated that implements each generated netlist on the programmable IC.