HLL-to-Hardware Debug Command Translation for FPGA Breakpoints
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Solution Overview
Problem
Debugging hardware accelerators, such as those implemented on FPGAs, is challenging due to the gap between software debugging environments and hardware debugging environments, where software designers are unfamiliar with signal-level debugging and need to navigate complex mappings between high-level language (HLL) and register transfer level (RTL) constructs.
Innovation Solution
A method and system that translate high-level language (HLL) debugging commands into hardware debugging commands, allowing a debug controller circuit on a programmable IC to execute breakpoints, read/write variables, and manage clock signals, while maintaining a cross-reference database to map HLL elements to RTL and hardware elements, enabling software-centric debugging of hardware accelerators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software designers use traditional hardware debugging methods with signal-level tracing, then they can debug hardware accelerators, but the debugging process becomes complex and difficult due to the need to navigate mappings between HLL and RTL constructs
Solution Approach 1:
The patent introduces an intermediary translation layer that converts high-level language debugging commands into hardware debugging commands. This intermediary system includes a command translator that maps HLL debugging operations (breakpoints, variable inspection) to corresponding hardware-level operations, shielding software designers from the complexity of direct hardware debugging while maintaining effective debugging capability
Solution Approach 2:
The debugging system is segmented into distinct functional components: an HLL debugging interface layer, a command translation layer, and a hardware debugging execution layer. This segmentation allows each layer to handle specific tasks independently, reducing the overall complexity for software designers who only need to interact with the familiar HLL interface
2Reliability
If software designers instrument hardware design with debug circuitry before synthesis, then debugging can be facilitated, but multiple synthesis iterations are necessary with each iteration involving changing the design and tracing different signals
Solution Approach 1:
The system performs preliminary translation of HLL debugging commands into hardware debugging commands before actual hardware execution. The command translator pre-processes debugging requests, identifying the appropriate hardware signals and operations needed, which eliminates the need for multiple synthesis iterations and trial-and-error debugging approaches
Solution Approach 2:
The debugging system implements a feedback mechanism where the results of hardware debugging operations are translated back into HLL constructs. This allows software designers to immediately see the results of their debugging actions in terms of familiar software variables and line numbers, enabling rapid iteration without time-consuming synthesis cycles
3Reliability
If designers specify debug circuitry to monitor individual signals, then hardware debugging can be performed, but the designer must know the internal low level signals to trace and the triggers to set
Solution Approach 1:
The system creates a virtual copy of the HLL debugging environment at the hardware level. Instead of requiring designers to directly manipulate hardware signals, the translation layer copies the familiar HLL debugging interface and automatically maps it to the appropriate hardware signals, eliminating the need for designers to learn internal signal names and trigger configurations
Data Source
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AI summary
An approach for debugging a circuit implementation of a software specification includes translating (508) a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation (108), and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted (518) to a debug controller circuit (112) that generates (624) a single clock pulse to the circuit implementation. The debug controller circuit reads (626) a value(s) from the storage element(s) specified by the hardware debugging command and determines (628) whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output (632) in response to the value(s) read from the storage element(s) satisfying the condition.