Hardware Debug Server Translating HLL Breakpoints to RTL Simulation
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Solution Overview
Problem
Software designers face challenges in debugging hardware accelerators due to the difference between software and RTL debugging environments, as they are unfamiliar with the RTL structure and the association between HLL program elements and signal names and registers, hindering timely debugging.
Innovation Solution
A system that bridges the gap between software and RTL debugging environments by using a hardware debug server to translate software debugging commands into hardware debugging commands, allowing software designers to set breakpoints and inspect variables in the HLL environment, while interacting with an RTL simulator to suspend execution and provide debug information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software designers use traditional RTL simulators to debug hardware accelerators, then debugging capability is available, but the learning curve and difficulty of operation increase significantly due to unfamiliarity with RTL structure and signal names
Solution Approach 1:
The patent introduces a translation layer that acts as an intermediary between software debugging commands and RTL simulation operations. This translation layer maps high-level language debugging commands to corresponding RTL simulation commands, allowing software designers to use familiar debugging tools without needing to learn RTL-specific syntax and concepts. The intermediary translates variable names to signal names, breakpoint locations to simulation time points, and maintains state correspondence between HLL and RTL representations.
2Loss of information
If software designers trace low-level signals and interpret waveforms in RTL simulators, then debugging information is obtained, but the time required for debugging increases due to the complexity of RTL structure
Solution Approach 1:
The patent creates and maintains a copy of the high-level language program state within the RTL simulation environment. This copy includes variable values, program counter positions, and execution state that mirror the original HLL program. By maintaining this parallel representation, debugging information can be extracted directly from the HLL-level copy rather than requiring analysis of complex RTL waveforms, significantly reducing debugging time while preserving complete debugging information.
Solution Approach 2:
The translation layer serves as an intermediary that automatically correlates RTL simulation events with HLL program events. It maps signal transitions to variable changes, simulation time to program execution points, and automatically generates debug information in terms of HLL variables rather than RTL signals. This mediation eliminates the manual effort required to interpret RTL waveforms while maintaining complete debugging information.
3Ease of operation
If breakpoints are set in HLL source code during RTL simulation, then software designers can use familiar debugging interfaces, but the system complexity increases due to the need for translation and correlation mechanisms
Solution Approach 1:
The debugging system implements self-service mechanisms where the translation layer automatically maintains the correspondence between HLL breakpoints and RTL simulation events without requiring manual intervention. The system automatically tracks variable mappings, correlates execution states, and manages breakpoint translation. This automation reduces the perceived complexity for users while the underlying translation infrastructure handles the complexity internally.
Data Source
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AI summary
Approaches for debugging include receiving (412) by a hardware debug server (106), a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates (414) the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input (414) to a simulator (108). The simulator adds (420) a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes (420, 426) a simulation of the finite state machine representation. Execution of the simulation is suspended (428) in response to the detecting the condition in the finite state machine.