Early Detection of Sequential Access Violations in HLS Array Simulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-level synthesis (HLS) workflows face challenges in detecting sequential access violations in array accesses, which are often identified late in the development process, leading to significant debugging and redesign time due to the lack of early detection during simulation.
Innovation Solution
A method and system for simulating applications in HLS that detect and determine whether array accesses occur in sequential order, using library code to track and check access sequences, allowing for early identification of sequential access violations before RTL translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-level simulation is performed using C/C++ before RTL translation, then functional verification is enabled, but sequential access violations in array accesses are not detected
Solution Approach 1:
The patent introduces an intermediary simulation model that sits between the C/C++ application and the RTL translation process. This model intercepts array access operations and verifies whether they follow sequential access patterns, enabling detection without modifying the original C/C++ code or waiting for RTL translation.
Solution Approach 2:
The patent performs sequential access validation during the high-level simulation phase, before RTL translation occurs. By checking array access patterns early in the design process, it prevents violations from carrying forward to later stages, enabling earlier detection and correction.
2Measurement precision
If sequential access validation is performed during RTL simulation, then access violations are detected, but significant debugging and redesign time is consumed
Solution Approach 1:
The patent moves the validation action to occur before RTL translation, during the high-level simulation phase. This preliminary detection allows developers to identify and fix sequential access violations while still working with high-level code, avoiding the need to debug complex RTL descriptions later.
Solution Approach 2:
The patent enables rapid validation of sequential access patterns during simulation without requiring full RTL translation and subsequent RTL simulation. This skipping of intermediate steps accelerates the detection process significantly.
3Adaptability or versatility
If array accesses are not constrained to sequential order, then C/C++ simulation flexibility is maintained, but incorrect RTL descriptions are generated
Solution Approach 1:
The patent implements a feedback mechanism during high-level simulation that monitors array access patterns and provides immediate feedback when non-sequential access is detected. This feedback allows developers to correct issues while maintaining C/C++ simulation flexibility, ensuring accurate RTL generation without restricting coding freedom.
Solution Approach 2:
The patent introduces an intermediary validation layer that sits between the flexible C/C++ array access operations and the RTL generation process. This intermediary checks access patterns and ensures correctness requirements are met while allowing the C/C++ simulation to remain flexible and unrestricted.
Data Source
AI summary
Detecting sequential access violations for high-level synthesis (HLS) includes performing a simulation, using computer hardware, of an application for HLS. During the simulation, accesses of the application to elements of an array of the application are detected. During the simulation, determinations of whether the accesses occur in a sequential order are made. An indication of whether the access occur in sequential order is generated.