High Level Synthesis Bypass Circuit for Dynamic Clock Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High level integrated circuit design faces challenges in modifying circuit configurations post-production due to low readability of hardware description languages (HDL), leading to inefficient power consumption and performance issues, as changing clock frequency or latency requires re-running high level synthesis, which is costly and difficult.
Innovation Solution
A design method that includes generating hardware descriptions with inter-stage registers and determining bypass stage selection patterns based on bypass constraint information, allowing for flexible configuration changes by generating bypass report information and integrating bypass setting circuits to adjust clock frequency and latency without re-synthesizing the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the behavioral description is converted to functional description in HDL, then the circuit configuration can be generated, but it becomes difficult to change the circuit configuration later due to low readability of HDL
Solution Approach 1:
The patent segments the circuit configuration into two layers: the functional description in HDL remains unchanged, while a separate configuration specification (in C/C++ or YAML) stores the circuit parameters. This allows independent modification of configuration parameters without changing the HDL code, resolving the contradiction between generating circuit configurations and enabling easy changes.
Solution Approach 2:
The patent introduces an intermediary configuration specification layer between the behavioral description and the functional description. This intermediary stores circuit parameters such as clock frequency, latency, and resource constraints in a readable format, allowing users to modify circuit configurations without directly editing HDL code, thus improving adaptability while maintaining manufacturability.
2Adaptability or versatility
If the high level synthesis is re-run to change circuit configuration, then the desired configuration can be achieved, but the development time and cost increase
Solution Approach 1:
The patent performs preliminary action by pre-defining circuit parameters and constraints in a configuration specification before the high level synthesis process. This allows users to quickly adjust configurations by modifying the specification file rather than re-running the entire synthesis flow, significantly reducing development time while maintaining configuration flexibility.
Solution Approach 2:
The patent enables parameter changes by storing circuit parameters (clock frequency, latency, resource constraints) in a configurable specification format. Users can modify these parameters directly in the specification file without re-synthesizing the entire circuit, allowing rapid configuration changes and reducing development time and cost.
3Productivity
If the clock frequency is increased to improve throughput, then the latency increases, but the power consumption increases and the circuit may not be necessary at such high speed
Solution Approach 1:
The patent implements dynamics by making the clock frequency and latency parameters configurable rather than fixed. The configuration specification allows users to dynamically adjust these parameters based on actual operational requirements, enabling the circuit to operate at optimal speeds and reducing unnecessary power consumption when high throughput is not required.
Solution Approach 2:
The patent applies parameter changes by allowing users to modify clock frequency and latency parameters in the configuration specification. This enables flexible adjustment of circuit performance characteristics, allowing optimization between throughput and power consumption by selecting appropriate parameter values without redesigning the circuit.
4Productivity
If the behavioral description is written in high level language, then the development speed increases, but the readability of the generated HDL decreases
Solution Approach 1:
The patent segments the design description into two distinct parts: the behavioral description in high-level language (C/C++) which maintains readability and development speed, and the configuration specification in a structured format (YAML or C/C++) which stores circuit parameters. This segmentation allows the HDL generation process to produce readable output by separating algorithmic logic from hardware-specific parameters.
Solution Approach 2:
The patent introduces an intermediary configuration specification that acts as a bridge between the high-level behavioral description and the generated HDL. This intermediary stores circuit parameters in a readable, structured format, allowing users to understand and modify hardware parameters without reading complex HDL code, thus maintaining readability while enabling high-level development.
Data Source
AI summary
A design method including a high level synthesis process that has (1) generating a hardware description of a circuit and high level synthesis report information from a source code based on a high level synthesis constraint, the hardware description describing a circuit including a plurality of stages and inter-stage registers; (2) determining a bypass stage selection pattern based on bypass constraint information including a constraint condition related to a bypass of the inter-stage register and the high level synthesis report information, the bypass stage selection pattern including a plurality of patterns each pattern having a combination of stages of inter-stage registers for which bypass setting is performed among stages of a bypass setting-capable inter-stage registers; and (3) generating bypass report information based on the bypass stage selection pattern, the bypass report information including combination information of the inter-stage registers for which the bypass is performed setting corresponding to a predetermined priority condition.