HLS Debugging System Mapping HLL to FSM States
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Solution Overview
Problem
Software designers face challenges in debugging hardware accelerators due to the gap between software debugging environments and RTL simulators, as they are unfamiliar with RTL and circuit structures, making it difficult to debug timing, concurrency, and implementation issues in hardware accelerators.
Innovation Solution
A debugging system that uses a cross-reference database to map high-level language (HLL) program elements to hardware language finite state machine elements, allowing software designers to debug hardware accelerators as if in a software debugger environment, by generating and storing mappings of HLL program elements to hardware language finite state machine states and lines, facilitating breakpoint setting and variable inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software designers use RTL simulators to debug hardware accelerators, then debugging capability is provided, but software designers face difficulty due to unfamiliarity with RTL and circuit structures
Solution Approach 1:
The patent introduces a debugging system that acts as an intermediary between software designers and RTL simulators. This system translates software-level debugging commands into hardware-level simulation operations, allowing designers to debug hardware accelerators using familiar software debugging interfaces while the system handles the complexity of RTL and circuit structure translations behind the scenes.
2Productivity
If hardware accelerators are implemented from HLL specifications, then performance is improved, but timing and concurrency issues may be masked during software development and surface during hardware simulation
Solution Approach 1:
The debugging system performs preliminary debugging actions by establishing breakpoints and inspecting variables at the software specification level before hardware simulation. This allows timing and concurrency issues to be identified and addressed during the software development phase, preventing them from surfacing later during hardware simulation and reducing rework.
3Loss of information
If software designers trace low-level signals and interpret waveforms in RTL simulators, then debugging information is obtained, but the process becomes complex and time-consuming
Solution Approach 1:
The debugging system creates a software-level copy or representation of the hardware accelerator's execution state. Instead of requiring designers to trace low-level signals and interpret waveforms directly in the RTL simulator, the system provides debugging information in terms of the original HLL program variables and statements, effectively copying the software debugging experience to the hardware debugging context and significantly reducing the time and complexity involved.
Data Source
AI summary
Disclosed approaches for configuring a memory include generating by a high-level synthesis (HLS) tool executing on a computer system, a first mapping of elements of a high-level language (HLL) program to elements of a hardware language finite state machine that represents a circuit implementation of the HLL program. The HLS tool further generates a second mapping of lines of the HLL program to states of the hardware language finite state machine and stores the information describing the first mapping and the second mapping in a data structure of a database in the memory.