Dynamic Memory Management for HLS on FPGA
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Solution Overview
Problem
Current dynamic memory management methods for FPGA platforms, such as Fixed Size, Bitmap, and Buddy System, are not suitable for managing GB-scale DRAM, leading to poor flexibility, low memory utilization, and inefficient allocation due to memory fragmentation and long traversal times.
Innovation Solution
A high-level-synthesis-oriented dynamic memory management apparatus comprising searching and caching modules connected to DRAM and BRAM buffers, utilizing a multi-way search tree structure for efficient memory allocation and deallocation, reducing coding workload and improving memory utilization by managing free blocks and avoiding backtracking traversals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If Bitmap method is used for memory management, then allocation and deallocation can be performed by looking up the vector, but in GB-scale memory space the vector becomes too long causing every allocation to traverse the entire vector resulting in poor allocation efficiency
Solution Approach 1:
The patent segments the long vector into multiple sub-vectors or blocks, each managing a portion of the memory space. This allows allocation operations to traverse only relevant sub-vectors rather than the entire vector, significantly reducing traversal time and improving allocation efficiency in GB-scale memory spaces.
Solution Approach 2:
The patent introduces an additional dimension by organizing memory management in a hierarchical structure with multiple levels of vectors. Instead of a single long vector, it uses a tree-like structure where higher-level vectors manage larger memory regions and lower-level vectors manage smaller regions, enabling faster location of free blocks through multi-level indexing.
2Productivity
If Buddy System uses tree structure to accelerate bitmap looking-up, then allocation efficiency improves, but clock frequency decreases greatly with the increase of the tree height preventing suitability for large DRAM
Solution Approach 1:
The patent optimizes the tree structure by making it balanced and ensuring that each node at the same level has similar properties and management responsibilities. This local uniformity allows for predictable timing behavior and maintains clock frequency while providing efficient allocation through the tree structure.
Solution Approach 2:
The patent uses a flattened or simplified tree structure that performs only the necessary allocation operations without excessive traversal. By implementing early termination conditions and optimizing the search path, it achieves sufficient allocation efficiency without requiring deep tree structures that would reduce clock frequency.
3Ease of manufacture
If Fixed Size method is used for memory allocation, then allocation process is simple, but it can only allocate memory blocks of fixed length resulting in poor flexibility and large number of memory fragments leading to low memory utilization
Solution Approach 1:
The patent implements dynamic memory block sizing where the allocation size is determined at runtime based on the actual needs of the application. The system maintains a pool of memory blocks with different sizes and dynamically selects appropriate blocks for allocation, providing both flexibility and reasonable simplicity in the allocation process.
Solution Approach 2:
The patent changes the parameter of memory block size from fixed to variable. It maintains a collection of free blocks with different sizes and selects the most appropriate block for each allocation request, thereby achieving flexibility in memory allocation while keeping the process relatively simple through predefined size categories.
4Reliability
If static memory allocation is used to replace dynamic memory management, then code refactoring is required and memory occupancy is maximized, but this leads to low memory efficiency and high hardware overheads
Solution Approach 1:
The patent implements a self-service memory management system where the hardware automatically handles dynamic memory allocation, deallocation, and fragmentation management without requiring software intervention or code refactoring. The memory management unit monitors and manages memory blocks autonomously, maintaining both code correctness and high memory efficiency.
Solution Approach 2:
The patent introduces a hardware memory management unit as an intermediary between the processor and the memory system. This intermediary handles all dynamic memory management operations, including allocation, deallocation, and consolidation of free blocks, thereby maintaining memory efficiency without requiring changes to the application code.
Data Source
AI summary
The present invention relates to a dynamic memory management apparatus and method for HLS, the apparatus has several searching and caching modules and several modifying and writing-back modules, the searching and caching modules are in connection with a DRAM storing module and a BRAM buffer, respectively, and the modifying and writing-back modules are in connection with the DRAM storing module and the BRAM buffer, respectively, the BRAM buffer is for caching information about nodes on a search path and registering information about modification made to the nodes. To remedy the defect that the traditional operating system is directly transplanted to the FPGA and has low execution efficiency, the present invention utilizes the advantage of the large capacity of the DRAM on the FPGA to realize efficient dynamic memory allocation and deallocation, and improve the usability and code reusability of HLS.