HLS Circuit Blocks Using FIFO Buffer Control
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Solution Overview
Problem
Conventional high-level synthesis (HLS) processing struggles with implementing circuit architectures for applications like frame-based video processing, where producer and consumer circuits have different memory access patterns, leading to delayed consumer operations and increased memory requirements.
Innovation Solution
The method involves partitioning an application array into virtual blocks based on streaming dimensions, using a FIFO memory to couple circuit blocks with shared access patterns, and incorporating control circuitry to manage concurrent operations through multiple buffers in the FIFO memory, allowing random access and reducing memory size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional HLS processing is used to implement circuit architectures for applications with different memory access patterns, then the implementation is simpler, but data throughput is reduced and latency is increased
Solution Approach 1:
The patent segments the memory access patterns by identifying producer and consumer circuits with different access patterns, then applies separate handling mechanisms (streaming memory for producers, random access memory for consumers) to each segment, enabling optimized data flow for each type while maintaining overall system functionality
Solution Approach 2:
The patent introduces an intermediary mechanism (streaming memory with control logic) between producer and consumer circuits to mediate their different access patterns, allowing producers to stream data efficiently while consumers access data randomly without directly conflicting with each other's requirements
2Loss of time
If conventional HLS processing is used for applications with different memory access patterns, then the design process is easier, but consumer operations are delayed
Solution Approach 1:
The patent performs preliminary action by pre-identifying producer and consumer circuits and their access patterns during the HLS design phase, then pre-configuring appropriate memory types and access control mechanisms for each circuit type before the actual data flow begins, eliminating runtime delays
Solution Approach 2:
The patent implements dynamic memory access control where the control logic adapts memory access patterns based on circuit type - streaming mode for producers and random access mode for consumers - allowing the system to dynamically optimize data flow characteristics for different operational phases and circuit requirements
3Quantity of substance
If conventional HLS processing is used, then fewer control mechanisms are needed, but memory requirements increase
Solution Approach 1:
The patent applies local quality by assigning different memory characteristics to different parts of the system - streaming memory with specific access control for producer circuits and random access memory for consumer circuits - allowing each local segment to have optimized memory properties suited to its specific access pattern requirements
4Productivity
If concurrent operation of circuit blocks is enabled, then productivity increases, but control complexity increases
Solution Approach 1:
The patent merges the control mechanisms for concurrent producer and consumer operations into a unified control structure that handles both streaming and random access patterns simultaneously, reducing overall control complexity by consolidating what would otherwise be separate control paths into a single integrated control unit
Data Source
AI summary
Implementing circuitry from an application may include partitioning an array of the application into a plurality of virtual blocks according to a streaming dimension of the array and determining that a first function and a second function of the application that access the array have same access patterns for the virtual blocks of the array. A first-in-first out (FIFO) memory may be included in a circuit design implementing the application. The FIFO memory couples a first circuit block implementing the first function with a second circuit block implementing the second function. Control circuitry is included within the circuit design. The control circuitry may be configured to implement concurrent operation of the first circuit block and the second circuit block by controlling accesses of the first circuit block and the second circuit block to a plurality of buffers in the FIFO memory.