High-Level Synthesis Inserting Functional Safety Into Control Dataflow Graphs
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Solution Overview
Problem
Conventional high-level synthesis methods fail to effectively implement functional safety systems in integrated circuit designs, as they delete redundant logic and do not accurately reflect the functional safety system described in the operation description, making it difficult to generate an RTL description that includes error countermeasures and functional safety systems.
Innovation Solution
A high-level synthesis method that generates an RTL description by inserting a functional safety system into the control dataflow graph using an operation description, a high-level synthesis script, and a functional safety system implementation specification, allowing for the explicit inclusion of functional safety systems in the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional high-level synthesis methods delete redundant logic during synthesis, then the synthesis process can be completed efficiently, but the functional safety system described in the operation description is not reflected in the RTL description
Solution Approach 1:
The patent segments the synthesis process into distinct phases: CDFG creation from operation description, functional safety system insertion into CDFG, scheduling, binding, and RTL generation. This segmentation allows functional safety logic to be preserved through targeted insertion in the CDFG phase before optimization, resolving the contradiction between synthesis efficiency and safety system implementation
Solution Approach 2:
The patent applies preliminary action by inserting the functional safety system into the CDFG before the main synthesis processes (scheduling, binding, optimization) occur. This ensures safety logic is established early and maintained throughout subsequent steps, preventing its deletion as redundant logic
2Reliability
If functional safety systems are inserted into the CDFG before scheduling and binding, then the RTL description includes error countermeasures, but the synthesis process complexity increases
Solution Approach 1:
The patent uses the CDFG (control dataflow graph) as an intermediary structure between the operation description and the final RTL description. Functional safety systems are inserted into this intermediate representation, which then guides the subsequent scheduling and binding processes. This intermediary approach manages complexity by providing a structured framework that integrates safety logic without overwhelming the synthesis process
Data Source
AI summary
Disclosed herein is a method of generating an RTL description that implements any functional safety system. A high-level synthesis method for generating an RTL description in which a functional safety system is inserted by using an operation description defining a functional logic, a high-level synthesis script defining a high-level synthesis constraint, and a functional safety system implementation specification specifying a functional safety system to be inserted in a high-level synthesis process. The high-level synthesis method includes a control data flow graph generation step in which a high-level synthesis unit generates a control data flow graph using the operation description, and a first function safety system insertion processing step in which the high-level synthesis unit inserts the function safety system into the control data flow graph according to the function safety system implementation specification after the control data flow graph generation step.