HLS Interface Mapping for Heterogeneous Hardware-Software Design
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Solution Overview
Problem
Traditional design flows for integrated circuits (ICs) with both hardware and software components are often limiting, as they require hardware designers to create a monolithic hardware design first, which does not account for software requirements or interface placement between subsystems, leading to decoupled hardware and software design processes that may not converge to a workable implementation.
Innovation Solution
A method that generates a logical architecture for an application, specifying a mapping of logical resources to hardware within an interface circuit block between data processing engines (DPE) arrays and programmable logic, allowing for the compilation and implementation of both hardware and software portions in a heterogeneous IC, using a processor to perform implementation flows and interface block constraint adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If hardware designers create a monolithic hardware design first, then the hardware design is complete and can serve as a platform for software design, but this approach is unduly limiting and does not account for software requirements or interface placement
Solution Approach 1:
The patent performs preliminary actions by generating a logical architecture and interface solutions before finalizing hardware and software implementations. The system creates a high-level representation of the application that identifies both hardware and software portions, then generates interface solutions that map logical resources to physical hardware resources. This preliminary architectural design allows software requirements to be considered during the hardware design phase, enabling iterative refinement and convergence of both designs rather than forcing a rigid monolithic hardware-first approach.
2Productivity
If hardware and software design processes are decoupled, then each can be developed independently, but there is no indication of software requirements or placement of interfaces between subsystems
Solution Approach 1:
The patent implements feedback mechanisms where the logical architecture generation and interface solution creation provide continuous information about software requirements and interface placements to both hardware and software design processes. The system generates interface solutions that specify mappings of logical resources to hardware resources, and this information feeds back to guide both hardware implementation and software compilation. This feedback loop ensures that decoupled design processes remain coordinated and that neither loses critical information about requirements or interface placements.
Solution Approach 2:
The patent introduces a logical architecture and interface solution generation system as an intermediary between hardware and software design processes. This intermediary component analyzes the application, generates a logical architecture that identifies hardware and software portions, and creates interface solutions that bridge the two domains. The intermediary maintains the connection between decoupled processes by providing interface placement information and software requirement specifications, enabling independent development while preserving essential coordination information.
3Ease of manufacture
If traditional monolithic hardware design is used, then hardware implementation is straightforward, but convergence with software design is poor and implementation quality is limited
Solution Approach 1:
The patent segments the application into distinct hardware and software portions through logical architecture generation. The system identifies which parts of the application are suitable for hardware implementation and which are better suited for software, creating a partitioned design that optimizes for both implementation simplicity and overall quality. This segmentation allows each portion to be implemented using the most appropriate methodology while maintaining clear interface definitions that ensure convergence and high implementation quality.
Solution Approach 2:
The patent introduces dynamic elements to the design process by enabling iterative refinement of the logical architecture and interface solutions. Rather than following a rigid monolithic hardware design approach, the system allows the logical architecture to be refined based on software requirements and interface constraints. The interface solutions can be adjusted and optimized, and the hardware and software portions can be re-evaluated and re-partitioned, providing the flexibility needed to achieve superior convergence and implementation quality while maintaining implementation simplicity.
Data Source
AI summary
For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.