High-Level Synthesis Loop Clustering for Circuit Design Optimization
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Solution Overview
Problem
Existing high-level synthesis (HLS) tools generate HLL code from block diagram circuit designs that result in inferior quality of results (QoR) compared to hand-written code, particularly in terms of clock frequency, resource utilization, latency, and throughput, due to optimizing individual tasks with low complexity.
Innovation Solution
The method involves generating a dependency graph from a block diagram representation, clustering vertices to combine multiple for-loops into a single for-loop, and optimizing each cluster rather than individual blocks, thereby reducing resource usage and improving QoR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If HLS tools optimize each task individually corresponding to blocks in the block diagram, then the design process is simple and automated, but the quality of results (QoR) is inferior compared to hand-written code
Solution Approach 1:
The patent merges multiple individual task optimizations into a unified optimization process. By clustering vertices in the dependency graph and combining their corresponding for-loops into a single optimized loop structure, the system achieves holistic optimization that surpasses individual task optimization while maintaining automated processing.
2Ease of manufacture
If multiple individual for-loops are generated for each block, then the code structure is simple and modular, but resource utilization and latency are suboptimal
Solution Approach 1:
The patent combines multiple separate for-loops into a single unified for-loop by clustering vertices in the dependency graph. This merging eliminates redundant loop overhead and reduces resource utilization while maintaining code generation simplicity through automated clustering algorithms.
3Ease of manufacture
If multiple individual for-loops are generated for each block, then the code structure is simple and modular, but latency and throughput are suboptimal
Solution Approach 1:
The patent merges multiple sequential for-loops into a single optimized loop structure, eliminating the time overhead of multiple loop initializations and terminations. This reduces latency while maintaining automated code generation through dependency graph-based clustering.
4Reliability
If unnecessary buffers are included in the generated code, then the code is more conservative and safer, but resource utilization increases and throughput decreases
Solution Approach 1:
The patent extracts and removes unnecessary buffer operations from the generated code by analyzing the dependency graph and identifying redundant memory operations. This elimination reduces resource utilization and improves throughput while maintaining code reliability through systematic dependency analysis.
Data Source
AI summary
Disclosed approaches include inputting a block diagram representation of a circuit design to a processor. Respective high-level programming language (HLL) code fragments associated with each block of the block diagram representation are determined. A dependency graph is generated from the block diagram representation. One or more clusters of vertices are generated from the dependency graph. Each of the HLL code fragments represented by the vertices of each cluster includes a for-loop, and each cluster includes a subset of the plurality of vertices and edges. For each of the clusters, a plurality of for-loops of the HLL code fragments associated with blocks represented by the vertices of the cluster are combined into a single for-loop. An HLL function is generated from each single for-loop and the HLL code fragments associated with each block that is not represented by any of the one or more clusters.