HLS Parameter Tuning for Loop Unrolling and Circuit Parallelism
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Solution Overview
Problem
In high-level synthesis for processing systems, there is a trade-off between performance per circuit and circuit parallel number, making it difficult to optimize resource usage and processing efficiency, particularly due to increased resource usage as performance improves and processing time overhead from state switching in multiple circuits.
Innovation Solution
A parameter optimization technique that determines an optimal combination of loop unrolling number and circuit parallel number by generating circuit synthesis information and calculating estimation processing performance based on resource constraints and delay constraints, allowing for maximum processing performance optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the loop unrolling number is increased to improve processing performance, then the processing speed is improved, but the resource usage in the processing system is increased
Solution Approach 1:
The patent applies parameter changes by systematically varying the loop unrolling number (a key parameter) to transform the processing system's performance characteristics. By changing this parameter across multiple candidate values, the system explores different performance-resource tradeoff points to find the optimal configuration.
Solution Approach 2:
The patent introduces dynamics by making the loop unrolling number adjustable and optimizable rather than fixed. The system dynamically selects from multiple candidate configurations based on performance estimates, allowing the processing system to adapt its resource allocation to achieve optimal performance.
2Productivity
If the circuit parallel number is increased to improve overall processing performance, then the total throughput is improved, but the usage of resources per circuit increases
Solution Approach 1:
The patent applies segmentation by dividing the processing system into multiple parallel circuits, each handling a portion of the overall workload. By segmenting the processing tasks across N parallel circuits, the system achieves higher throughput while managing resource distribution across multiple independent processing units.
Solution Approach 2:
The patent applies universality by designing parallel circuits that can handle multiple packet flows simultaneously. Each processing circuit is configured to process different flows of packets, making the system versatile in handling various input scenarios while maintaining efficient resource utilization across all circuits.
3Productivity
If multiple processing circuits are used to improve processing capacity, then the system throughput is improved, but processing time overhead occurs due to state switching
Solution Approach 1:
The patent applies preliminary action by pre-configuring the loop unrolling number and circuit parallel number before actual packet processing begins. This preliminary optimization phase allows the system to prepare the best configuration in advance, avoiding time-consuming adjustments during runtime and reducing processing overhead.
Solution Approach 2:
The patent applies feedback by using performance estimation to evaluate different configuration candidates and selecting the optimal one. The estimation mechanism provides feedback on expected performance, allowing the system to choose configurations that minimize processing time overhead while maximizing throughput.
Data Source
AI summary
An optimum combination of a loop unrolling number and a circuit parallel number in a high-level synthesis is determined. A circuit synthesis information generation unit sets, as parameter candidates, a plurality of combinations of a loop unrolling number and a circuit parallel number to generate circuit synthesis information indicating a synthesis circuit obtained by high-level synthesis processing for each of the combinations. An optimum parameter determination unit calculates, for each piece of the generated circuit synthesis information, an estimation processing performance related to the synthesis circuit indicated by the circuit synthesis information, and determines an optimum combination of the loop unrolling number and the circuit parallel number based on the circuit synthesis information based on which a maximum estimation processing performance is obtained.