High-Level Synthesis Module Division for Circuit Configuration
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Solution Overview
Problem
In high-level semiconductor design, defining modules in source code is challenging, especially when logic exists between multiple loop descriptions, as current tools lack clear criteria for merging non-loop logic with loop descriptions, leading to increased design complexity and labor.
Innovation Solution
A high-level synthesis device that extracts loop descriptions capable of merging with logical descriptions, calculates circuit characteristics, and determines the appropriate loop description to merge with, allowing for automatic and optimal module division.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the designer manually determines memory configuration and modifies source code to achieve desired circuit design, then the circuit scale and performance can be optimized, but the design complexity and required hardware knowledge increase
Solution Approach 1:
The high-level synthesis device automatically determines memory configuration and performs module division without requiring manual intervention. The system analyzes the behavioral description, identifies loop descriptions, and autonomously decides on memory types and quantities, eliminating the need for designers to manually modify source code while maintaining optimal circuit configuration.
Solution Approach 2:
The high-level synthesis device acts as an intermediary between the behavioral description and the final circuit implementation. It translates high-level loop descriptions into optimized RTL code with appropriate memory configurations, bridging the gap between abstract algorithmic descriptions and concrete hardware implementation without requiring direct designer intervention in the intermediate steps.
2Productivity
If the designer manually divides modules and designs data transfer between modules, then data transfer efficiency and latency can be optimized, but the design time and labor increase
Solution Approach 1:
The high-level synthesis device automatically performs module division and optimizes data transfer between modules. It analyzes the behavioral description, identifies independent loop descriptions, and autonomously creates optimal module boundaries and data transfer paths, eliminating manual design efforts while achieving high data transfer efficiency and minimized latency.
Solution Approach 2:
The patent replaces the manual mechanical process of module division and data transfer design with an automated computational system. The high-level synthesis device uses algorithms to analyze dependencies, determine optimal module boundaries, and generate efficient data transfer paths, substituting human cognitive and manual work with automated software-based analysis and synthesis.
3Ease of operation
If loop descriptions are treated as separate modules, then the design process becomes simpler to understand, but the number of modules increases leading to increased delay and design labor
Solution Approach 1:
The high-level synthesis device merges adjacent loop descriptions that can be executed independently into single modules. By analyzing the behavioral description and determining that certain loop descriptions have no data dependencies between them, the system combines multiple loops into one module, reducing the total number of modules while maintaining design simplicity and understanding.
4Reliability
If more modules are created to handle complex logic between loop descriptions, then the circuit functionality is more accurately represented, but the circuit scale and complexity increase
Solution Approach 1:
The high-level synthesis device merges loop descriptions with adjacent logical descriptions into integrated modules. By combining the loop structure with the logical operations that occur between loops, the system accurately represents the circuit functionality while avoiding the creation of separate, additional modules that would increase circuit scale and complexity.
Data Source
AI summary
A high-level synthesis device executes high-level synthesis on a behavioral description including a plurality of loop descriptions and a logical description. An extraction unit extracts loop descriptions that can be merged with the logical description without changing a function, as loop description candidates, from the plurality of loop descriptions. The extraction unit also calculates characteristics of a circuit of a case where the logical description is merged with each of the loop description candidates, as circuit characteristics. A determination unit determines a loop description to be merged with the logical description, from the loop description candidates based on the circuit characteristics. A merge unit merges the logical description with the loop description determined by the determination unit.