High-Level Synthesis Parallel Hardware Inference
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Solution Overview
Problem
Existing high-level synthesis (HLS) tools in electronic design automation (EDA) require significant hardware design skills and are not user-friendly for software programmers, limiting their usability in generating production-quality register-transfer level (RTL) code for semiconductor circuits.
Innovation Solution
A computer-implemented method and system that automatically infers parallel hardware RTL from multi-threaded software programs, specifically using C++ threads, to generate streaming hardware modules with FIFO interfaces, enabling software engineers to specify hardware behavior using familiar software techniques and exploiting spatial parallelism in FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional HLS tools are used to generate RTL code, then hardware circuit implementation is achieved, but significant hardware design skills are required reducing usability
Solution Approach 1:
The patent introduces C++ threads as an intermediary layer between software programming and hardware design. Software programmers use familiar C++ threading constructs to specify parallelism, which the HLS tool automatically translates into hardware parallelism without requiring direct hardware design knowledge. This mediator (C++ thread abstraction) bridges the gap between software ease-of-use and hardware functionality.
Solution Approach 2:
The patent replaces manual hardware design mechanisms (RTL coding, circuit design) with software-based mechanisms (C++ threading). Instead of mechanically constructing hardware descriptions using HDL, programmers use software threading abstractions that are automatically synthesized into hardware, substituting the mechanical hardware design process with a software-oriented approach.
2Adaptability or versatility
If software programmers use HLS tools, then hardware design accessibility is improved, but automatic inference of parallel hardware from software threads is limited
Solution Approach 1:
The HLS tool is enhanced to automatically infer parallel hardware architecture from C++ thread structures without requiring explicit hardware directives from the programmer. The tool self-services by analyzing the software thread graph, detecting parallelism opportunities, and automatically generating the corresponding hardware RTL code, reducing the need for manual hardware specification.
Solution Approach 2:
The patent changes the abstraction parameter from explicit hardware control signals to software thread characteristics. By monitoring software-level parameters (thread creation, synchronization, execution flow), the HLS tool automatically infers hardware parameters (parallelism degree, pipeline stages, resource allocation), transforming the design specification from hardware-centric to software-centric parameters.
3Productivity
If multi-threaded software programs are used to specify hardware, then spatial parallelism is exploited, but synchronization and resource sharing require additional hardware logic
Solution Approach 1:
The patent performs preliminary analysis of C++ thread synchronization requirements during the HLS compilation phase. The tool pre-detects mutex locks, barriers, and other synchronization primitives in the software code, and automatically generates the corresponding hardware synchronization logic before RTL code generation. This preliminary action ensures that synchronization hardware is efficiently integrated without requiring additional manual design effort.
Data Source
AI summary
A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving a multi-threaded software program with at least one C++ thread; generating a register-transfer level (RTL) hardware description of the at least one C++ thread; and automatically inferring generation of parallel hardware RTL in response to receiving the at least one C++ thread.