High Level Synthesis Port Architecture for Parallelism Extraction
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Solution Overview
Problem
High-level synthesis of integrated circuits faces challenges in extracting parallelism from programming language descriptions with complex constructs like loops and arrays, making it difficult to generate efficient circuit designs.
Innovation Solution
A computer-implemented method determines function relationships and generates non-self-synchronized ports with local memory and control circuitry for handshake signaling, allowing data flow between circuit blocks in accordance with control flow constructs, thereby facilitating parallelism and resource optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-level synthesis tools process complex programming language constructs (loops, arrays), then the ability to extract parallelism and improve system performance is enhanced, but the complexity of extracting dataflow architecture and generating circuit designs increases significantly
Solution Approach 1:
The patent segments the complex control flow construct into multiple independent components: control signal generation logic, dataflow graph extraction modules, and circuit block generation units. Each component processes specific aspects of the high-level language description independently, reducing the overall complexity of extracting parallelism from complex constructs like loops and arrays.
Solution Approach 2:
The patent introduces an intermediate dataflow graph representation that serves as a mediator between the high-level programming language description and the final circuit design. This intermediate representation simplifies the extraction process by providing a structured format that explicitly captures parallelism opportunities without requiring direct complex analysis of the original programming constructs.
2Adaptability or versatility
If non-self-synchronized ports with local memory are generated to handle data-dependent timing, then synchronization flexibility and resource usage are improved, but the device complexity and control circuitry requirements increase
Solution Approach 1:
The patent implements self-service mechanisms where the local memory associated with each non-self-synchronized port automatically manages its own synchronization state and data buffering. The control circuitry generates standardized handshake signals that work uniformly across all ports, reducing the overall control complexity despite the increased adaptability of individual ports.
Solution Approach 2:
The patent changes the synchronization parameter from self-synchronized to non-self-synchronized for specific ports based on data-dependent timing requirements. This parameter change allows flexible adaptation to different timing scenarios while maintaining a unified control framework through standardized handshake protocols, balancing adaptability with control simplicity.
3Manufacturing precision
If handshake signaling is implemented for non-self-synchronized ports, then data flow control accuracy is improved, but the number of control signals and communication overhead increase
Solution Approach 1:
The patent merges the handshake signaling mechanism into a unified control framework that is applied consistently across all non-self-synchronized ports. By combining multiple control functions into a single standardized handshake protocol, the patent reduces the effective number of independent control signals while maintaining precise data flow control through the coordinated interaction of request and acknowledgment phases.
Data Source
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AI summary
Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description (210, 215, 220). The second function is determined to be a data consuming function of the first function (225). Within a circuit design, a port including a local memory is automatically generated (240). The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.