High-Level Synthesis for RISC-V SoC FPGA Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of high-performance System-on-Chip (SoC) designs for Field Programmable Gate Arrays (FPGAs) is hindered by the lack of hardware expertise among software engineers, who struggle with hardware description languages and data transfer complexities, particularly with large data transfers and non-contiguous memory regions, making it difficult to effectively utilize FPGA fabric and interface hardware components.
Innovation Solution
A system that uses high-level synthesis (HLS) to generate RISC-V SoC designs, allowing software engineers to compile code into hardware descriptions and binaries, with automatic data transfer management between processors and accelerators, enabling the use of reconfigurable hardware and DMA engines to handle data transfers efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software engineers use traditional FPGA development methods requiring hardware description languages, then hardware functionality can be implemented, but the complexity and difficulty of operation increases significantly for software engineers without hardware expertise
Solution Approach 1:
The patent replaces the mechanical process of manually writing hardware description languages with an automated software compilation system. The high-level synthesis tool automatically translates C/C++ code into hardware description language (Verilog/VHDL) and generates the corresponding FPGA circuit design, eliminating the need for software engineers to manually work with complex HDL syntax and hardware design concepts.
Solution Approach 2:
The patent introduces a high-level synthesis tool as an intermediary between the software engineer's C/C++ code and the FPGA hardware implementation. This intermediary automatically performs the complex translation and optimization processes, managing the interface between software and hardware domains without requiring the software engineer to understand hardware description languages or FPGA architecture details.
2Reliability
If manual data transfer configuration is used between processor and hardware accelerators, then data transfer can be implemented, but the time and error rate of integration increases
Solution Approach 1:
The patent enables the system to automatically configure and manage data transfers between the processor and hardware accelerators. The high-level synthesis tool automatically generates the necessary data transfer interfaces, memory-mapped I/O configurations, and control logic based on the C/C++ code structure, allowing the system to self-configure without manual intervention and reducing both integration time and potential configuration errors.
3Productivity
If DMA engines are used for large data transfers, then transfer efficiency improves, but the complexity of configuring DMA engines and managing memory regions increases
Solution Approach 1:
The patent replaces the manual configuration process of DMA engines with automated code analysis and transformation. The high-level synthesis tool analyzes the C/C++ code to identify large data transfer operations and automatically generates the appropriate DMA configuration, memory region allocations, and transfer control logic, eliminating the need for engineers to manually configure complex DMA parameters and manage memory regions.
4Productivity
If hardened processors with operating systems are used, then processing capability improves, but the difficulty of ensuring contiguous memory regions for DMA transfers increases
Solution Approach 1:
The patent introduces the high-level synthesis tool as an intermediary that manages the complexity of memory region management. The tool analyzes the C/C++ code to determine the memory access patterns and data transfer requirements, then automatically generates the appropriate memory region configurations and DMA setup code, handling the complexity of ensuring contiguous memory regions without requiring the software engineer to manually manage memory allocation and contiguity.
Data Source
AI summary
An article of manufacture includes a medium with instructions that when read and executed by a processor, cause the processor to identify a code stream to be executed by a system-on-a-chip (SoC). The SoC is to include an open standard processor and hardware accelerators implemented in reprogrammable hardware. The processor is to, from the code stream, identify a first portion of the code stream to be executed as software by the open standard processor and a second portion to be executed in the accelerators, compile the first portion into a binary for execution by the open standard processor, and generate a hardware description for the second portion to be implemented by the hardware accelerators. The hardware description and the binary are to exchange data during execution of the code stream.