High-Level Synthesis Safety Feature Integration
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Solution Overview
Problem
Design flows that directly specify safety features using high-level synthesis languages in electronic design automation are prone to errors, inefficiencies, and increased costs, particularly in critical applications like automotive and aerospace, where safety is paramount.
Innovation Solution
A high-level synthesis tool that compiles algorithmic descriptions of circuit designs, identifying safety-critical constructs and generating safety features in a lower-level representation, such as RTL, using safety data types and pragmas, to integrate safety features without manual intervention, ensuring reliability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuit designers directly specify safety features using high level synthesis languages, then safety considerations and protections are improved, but the design process becomes prone to error, ineffective, insufficient, inefficient or too costly in terms of time or monetary expense
Solution Approach 1:
The patent introduces an intermediary compilation process that automatically translates high-level algorithmic descriptions containing safety constructs into low-level circuit designs with integrated safety features. This intermediary compiler acts as a mediator between the designer's high-level intent and the final hardware implementation, automatically generating safety mechanisms without requiring manual specification at the low level.
Solution Approach 2:
The patent implements preliminary action by incorporating safety data type definitions and safety constructs into the high-level algorithmic description before compilation. The compiler then processes these predefined safety constructs during the compilation phase, generating the corresponding safety features in the final circuit design before deployment, eliminating the need for post-design safety additions.
2Reliability
If circuit designers directly specify safety features using high level synthesis languages, then safety considerations and protections are improved, but the design process becomes too costly in terms of time or monetary expense
Solution Approach 1:
The patent enables self-service by allowing the compilation process to automatically generate safety features without requiring manual intervention from designers. The compiler autonomously processes safety constructs in the high-level code and produces the corresponding safety mechanisms in the low-level design, reducing the need for expensive manual safety feature specification and verification.
3Adaptability or versatility
If manual specification of safety features is used, then design flexibility is maintained, but the process is prone to error and inefficient
Solution Approach 1:
The compiler serves as an intermediary that preserves design flexibility by accurately translating high-level algorithmic descriptions with safety constructs into low-level implementations. It maintains the designer's intended functionality while automatically ensuring correctness through systematic translation of safety data types and constructs, reducing errors without sacrificing flexibility.
Data Source
AI summary
This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.


