High-Level Synthesis Tool Segmentation for RTL Generation
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Solution Overview
Problem
High-level synthesis tools face challenges in generating register-transfer level (RTL) code for hardware accelerators, particularly with complex and data-dependent arithmetic coding, leading to failures and excessive debugging/testing in hardware accelerator designs.
Innovation Solution
A method involving a high-level synthesis (HLS) tool that isolates and synthesizes a portion of source code, generates an RTL description, defines a library component based on this description, and replaces the original source code with the library component to facilitate efficient RTL generation, thereby reducing debugging and testing efforts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high-level synthesis tools are used to generate RTL code for hardware accelerators, then testing and changing RTL hardware becomes efficient, but synthesis failures occur due to complex arithmetic coding
Solution Approach 1:
The patent segments the source code into multiple modules, synthesizing each module separately into RTL code. This modular approach isolates synthesis failures to specific modules rather than the entire system, making debugging more efficient and improving overall synthesis reliability while maintaining the benefits of high-level synthesis.
2Ease of operation
If high-level synthesis is used for complex arithmetic coding, then debugging and testing becomes easier, but excessive debugging and testing is required due to synthesis failures
Solution Approach 1:
By dividing the system into synthesizable modules, the patent enables targeted debugging of only the problematic modules rather than the entire system. This reduces the time and effort required for debugging while preserving the ease of operation benefits provided by high-level synthesis.
Solution Approach 2:
The patent performs preliminary synthesis of individual modules before integrating them into the complete system. This preliminary action identifies and resolves synthesis issues early in the design process, preventing cascading failures that would require extensive debugging later.
3Adaptability or versatility
If arithmetic coding is implemented in RTL, then hardware accelerator functionality is achieved, but the non-linear and data-dependent nature of the algorithm causes synthesis failures
Solution Approach 1:
The patent applies segmentation by breaking down the complex arithmetic coding algorithm into smaller, more manageable functional modules that can be synthesized independently. This reduces the immediate synthesis complexity while maintaining the algorithm's adaptability and versatility through modular reconfiguration.
Data Source
AI summary
A non-transitory computer-readable storage medium having stored thereon computer executable program code which, when executed on a computer system, causes the computer system to perform steps is disclosed. The steps include receiving a portion of a source code including a first program model defining an element of an integrated circuit, generating a first register-transfer level (RTL) description based on the portion of the source code, defining a library component based on the first RTL description, receiving the source code including a second program model defining the integrated circuit, replacing the portion of the source code corresponding to the first program model with the library component, and generating a second RTL description based on the source code.