H-Matrix Error Coding for Fast 2-Bit Memory Error Handling
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Solution Overview
Problem
Existing error correction and detection methods for data stored in memory are inefficient in correcting 1-bit errors and adjacent 2-bit errors while requiring excessive check bits for nonadjacent 2-bit error detection.
Innovation Solution
The use of an error code with an H-matrix having distinct columns and XOR sums, where the number of components in a column is less than 2·log2 n, allowing for efficient correction of 1-bit errors and adjacent 2-bit errors, and detection of nonadjacent 2-bit errors with reduced check bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 2-bit-error-correcting BCH codes are used, then error correction capability is improved, but processing speed decreases and number of check bits increases
Solution Approach 1:
The patent segments the error correction task into two distinct parts: a simplified correction stage for 1-bit and adjacent 2-bit errors using a reduced H-matrix, and a detection stage for nonadjacent 2-bit errors. This segmentation allows the correction process to use fewer check bits and simpler logic, significantly improving processing speed while maintaining reliable correction capability for the most common error types.
Solution Approach 2:
The patent changes the parameters of the H-matrix by reducing the number of check bits from what would be required for full 2-bit error correction. The H-matrix is specifically designed with columns that satisfy XOR sum properties, enabling the system to operate with fewer check bits while still achieving effective correction for 1-bit and adjacent 2-bit errors through the modified correction logic.
2Reliability
If traditional 2-bit-error-correcting BCH codes are used, then error correction capability is improved, but number of check bits increases
Solution Approach 1:
The patent extracts and separates the correction function for 1-bit and adjacent 2-bit errors from the full 2-bit error correction capability. By taking out only the essential correction functionality needed for the most frequent error types and implementing it with a reduced H-matrix, the system achieves effective error correction with significantly fewer check bits, reserving the remaining check bits for detection of less common nonadjacent 2-bit errors.
3Productivity
If simplified error correction methods are used, then processing speed is improved, but error correction capability decreases
Solution Approach 1:
The patent implements dynamic error handling by providing different correction paths: a fast correction path for 1-bit and adjacent 2-bit errors using the reduced H-matrix, and a detection-only path for nonadjacent 2-bit errors. The system dynamically selects the appropriate path based on the error syndrome, achieving both high processing speed for common errors and maintained reliability through detection capability for more complex error patterns.
Data Source
AI summary
A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.