Host Memory Buffer Boot Loading with Real-Time Latency Switching
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Solution Overview
Problem
Existing data storage devices face challenges in optimizing boot code latency when both host memory buffer (HMB) and internal memory (NAND) store the same data, as they often rely on a single location for boot code access, leading to inefficiencies due to varying access latencies.
Innovation Solution
A data storage device controller is configured to track turnaround latency of both HMB and NAND devices, allowing it to selectively receive boot code chunks from the faster location and periodically confirm delivery speed to optimize latency, ensuring efficient boot code access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If boot code is stored in HMB, then throughput is high and availability may be improved, but access latency becomes unpredictable and depends on host device availability
Solution Approach 1:
The controller monitors HMB access performance and uses this feedback to dynamically adjust boot code loading strategy. When HMB access latency exceeds thresholds or availability is compromised, the system switches to loading boot code from NAND memory, ensuring predictable boot timing regardless of HMB performance variations
Solution Approach 2:
The system dynamically selects between HMB and NAND for boot code storage based on real-time conditions. The boot code location is not fixed but adapts according to HMB availability and performance, allowing the system to optimize between throughput benefits of HMB and latency predictability of NAND
2Reliability
If boot code is stored in NAND, then availability is guaranteed and parallel sense can occur on multiple dies, but sense time increases boot latency
Solution Approach 1:
The system merges the advantages of both HMB and NAND by loading boot code from both locations simultaneously. The controller initiates parallel read operations to both HMB and NAND, then selects the faster source, combining the high throughput capability of HMB with the guaranteed availability of NAND
Solution Approach 2:
The system performs preliminary checks to determine HMB availability and performance characteristics before committing to a boot code loading strategy. This preliminary assessment allows the system to prepare the optimal loading path in advance, reducing actual boot latency
3Productivity
If the controller always checks HMB availability before accessing boot code, then optimal performance can be achieved, but additional latency is introduced during the check process
Solution Approach 1:
HMB availability and performance characteristics are checked in advance during system initialization or idle periods, before boot code access is required. This preliminary assessment caches the HMB status information, so that during actual boot operations, the controller can make decisions based on pre-evaluated data without introducing additional check latency
Solution Approach 2:
The system performs self-assessment of HMB capability and maintains this information for future decisions. The controller learns from past HMB performance and uses this knowledge to optimize boot code loading strategy without requiring repeated checks, reducing overhead while maintaining efficiency
Data Source
AI summary
Boot code is loaded to the data storage device controller in a flexible manner by being able to receive chunks of the boot code from two separate locations, the host memory buffer (HMB) and the memory device, which may be a NAND device. Part of the boot code may be received from the HMB and another part of the boot code may be received from the memory device. If either the HMB or the memory device can deliver the chunks faster than the other, then the controller can receive the chunks from the faster location and periodically confirm the speed of delivery to ensure the boot code latency is optimized. The controller is configured to track an HMB turnaround latency and derive whether a next request should be sent to the HMB or the memory device when the data is present in both the HMB and the memory device.