HMB Cache for SSD L2P Mapping Table

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Solution Overview

Problem

Traditional SSD architectures face challenges in efficiently managing the Flash Translation Layer (FTL) address mapping table, as DRAM-based solutions increase costs while NAND-based solutions incur high access latency.

Innovation Solution

The proposed method utilizes Host Memory Buffer (HMB) as a cache for the physical address mapping table, dividing the HMB into sections and using metadata to efficiently manage and update L2P mapping entries, thereby improving access performance and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If DRAM is used to store the L2P mapping table, then access latency is reduced, but manufacturing cost increases

Engineering Contradiction:
Improveaccess latencyVSAvoidmanufacturing cost
Core Design Contradiction:
Loss of timeVSEase of manufacture

Solution Approach 1:

The patent introduces HMB as an intermediary memory buffer between the host and SSD. The HMB is allocated from host system memory and used to cache frequently accessed L2P mapping entries, thereby reducing access latency without requiring expensive DRAM on the SSD side. This mediator approach allows the system to benefit from fast memory access while avoiding the cost of on-SSD DRAM.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a caching strategy where only frequently accessed (hot) L2P mapping entries are stored in the HMB buffer, while less frequently accessed (cold) entries remain in NAND flash. This local quality differentiation optimizes the system by providing fast access for hot data while maintaining cost efficiency for cold data storage.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If HMB is used to store the L2P mapping table, then cost is reduced, but access latency increases compared to DRAM

Engineering Contradiction:
Improvemanufacturing costVSAvoidaccess latency
Core Design Contradiction:
Ease of manufactureVSLoss of time

Solution Approach 1:

The patent pre-loads frequently accessed L2P mapping entries into the HMB buffer before they are actually needed for data access operations. By anticipating which entries will be needed and loading them in advance, the system minimizes the latency penalty of using HMB instead of DRAM, as the data is already in the faster memory when needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuous updates to the HMB cache as L2P mapping entries change, ensuring that the cache remains synchronized with the actual mapping table in NAND flash. This continuous maintenance of cache validity ensures that the HMB approach remains effective over time as data access patterns evolve.

Inventive Principle:
Principle #20Continuity of useful action

3Ease of manufacture

If HMB space is limited, then cost is reduced, but the ability to store entire L2P mapping table is compromised

Engineering Contradiction:
ImprovecostVSAvoidstorage capacity for L2P entries
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent divides the L2P mapping table into segments based on access frequency, with hot entries stored in HMB and cold entries stored in NAND flash. This segmentation allows the limited HMB space to be used most effectively for high-priority data while maintaining the complete mapping table across both storage media.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic cache management where the contents of HMB are continuously updated based on changing access patterns. As data is written or deleted from the SSD, the corresponding L2P entries are updated in both NAND flash and HMB cache, ensuring the cache adapts to current needs while working within limited space constraints.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12287737B2Method and system of using HMB as a cache of physical address mapping table
Publication Date: 2025.04.29 INNOGRIT TECH CO LTD
  • US12287737B2 patent drawing
  • US12287737B2 patent drawing
  • US12287737B2 patent drawing

AI summary

This application discloses a method and system of using HMB as a cache of physical address mapping table. The method comprises: arranging physical addresses in order of logical addresses, physical mapping entries corresponding to a plurality of consecutive physical addresses form one table unit, and a logical address corresponding to a first entry of each table unit is used as an index of the table unit; determining HMB size, dividing all table units into a plurality of sections according to the HMB size, each section comprises a plurality of table units, each section is divided into a plurality of ways; calculating a metadata according to logical address corresponding to the first entry of the table unit to be stored and the HMB size, the metadata comprises a section number and a way number; writing the metadata and the table unit to be stored into the HMB. This application uses HMB as L2P address mapping table cache of SSD controller, saving or avoiding use cost of DRAM on SSD, and reducing SSD size.