HMC Controller Wait Mode for Low Power Transitions
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Solution Overview
Problem
Existing HMC systems face power consumption issues due to high-speed serial links remaining active for synchronization, leading to packet loss when switching to sleep mode, and performance degradation from lengthy mode switching times.
Innovation Solution
Implementing a CPU and HMC side controller with a wait mode that checks buffer emptiness before switching to sleep mode, using check packets to ensure no packet loss and minimizing performance degradation by adjusting link states based on bandwidth calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the high-speed serial link remains active for synchronization, then link stability is maintained, but power consumption increases
Solution Approach 1:
The link dynamically switches between active mode and sleep mode based on data transmission requirements. When no data is transmitted for a predetermined period, the link transitions to sleep mode to reduce power consumption while maintaining the ability to quickly resume active mode when needed.
Solution Approach 2:
The system changes the operational parameters of the link by adjusting the synchronization signal transmission frequency and timing. During sleep mode, the link maintains basic synchronization with reduced activity, allowing power savings while preserving link stability for quick reactivation.
2Use of energy by moving object
If the link switches to sleep mode to reduce power consumption, then power efficiency improves, but packet loss occurs
Solution Approach 1:
Before switching to sleep mode, the system transmits a wake-up packet to ensure any pending data is flushed through the link. This preliminary action prevents packet loss by clearing the buffer before the link enters low-power state.
Solution Approach 2:
The system uses acknowledgment packets and buffer status monitoring to provide feedback about data transmission state. This feedback mechanism ensures that the link only enters sleep mode when it is safe to do so, preventing packet loss by confirming all data has been transmitted.
3Use of energy by moving object
If the link switches between active and sleep modes, then power consumption is reduced, but mode switching time degrades performance
Solution Approach 1:
The system enters sleep mode after a predetermined period of no data transmission, creating a periodic pattern of active and sleep states. This predictable timing allows the system to optimize the balance between power savings and performance impact.
Solution Approach 2:
The system uses wake-up packets and priority handling to rush through the mode transition process as quickly as possible. By prioritizing the resumption of active mode when data transmission is needed, the system minimizes the performance impact of mode switching.
4Use of energy by moving object
If all links switch to sleep mode simultaneously, then power consumption is maximally reduced, but link availability decreases
Solution Approach 1:
The system segments the link group into multiple independent links that can operate in different modes simultaneously. This allows some links to remain active while others enter sleep mode, providing both power savings and maintained availability for different data streams.
Solution Approach 2:
Each link is independently controlled with its own sleep/active state based on its specific data transmission needs. This local control allows optimal power management for each link while maintaining overall system availability through differentiated link states.
Data Source
AI summary
Disclosed are an HMC controller and a controlling method on a CPU side and an HMC side for a low power mode, and a recording medium related thereto. The CPU side HMC controller includes a plurality of link units, each of which includes a link master for storing request packets of a CPU in a request buffer and transmitting the request packets to an HMC side HMC controller in the order that they are stored; and a link slave for storing the request packets received from the HMC side HMC controller in a response buffer and transmitting the request packets to the CPU in the order that they are stored.


