Head-Mounted Display Semiconductor Substrate Through Hole Reduction

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Solution Overview

Problem

Existing head-mounted display (HMD) devices face challenges in achieving high-resolution images while minimizing the area occupied by through holes, which connect different semiconductor substrates, thereby complicating the integration of high-density circuitry.

Innovation Solution

The use of two different monocrystalline semiconductor substrates, where the second substrate has a larger planar area than the first, allows for the reduction of through holes by distributing circuit parts between the substrates and using a connection wiring layer to connect conductive vias.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple through holes are used to connect different semiconductor substrates, then electrical connection between substrates is achieved, but the area occupied by through holes increases

Engineering Contradiction:
Improveelectrical connectionVSAvoidarea occupied by through holes
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent divides the through holes into two distinct types: first through holes for connecting data lines to subpixels, and second through holes for connecting the gate-driving part to subpixels. This segmentation allows for optimized placement and reduced total area by organizing connections functionally rather than using a uniform connection approach.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes the thickness direction (vertical dimension) by forming through holes that penetrate the second semiconductor substrate to reach the first substrate. This three-dimensional connection approach reduces the need for lateral routing and minimizes the planar area occupied by connection structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the semiconductor substrate area is increased to accommodate high-resolution circuitry, then integration density is improved, but the overall device size increases

Engineering Contradiction:
Improveintegration densityVSAvoidsubstrate area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent segments the circuit functionality across two different semiconductor substrates: the first substrate contains the gate-driving part while the second substrate contains the display area with subpixels. This segmentation allows each substrate to be optimized for its specific function, achieving high integration density without requiring a single large substrate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a stacked configuration where the first semiconductor substrate is positioned beneath the second semiconductor substrate, with connection structures penetrating through the second substrate to reach the first. This nested, three-dimensional arrangement enables high integration density while maintaining a compact overall footprint.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentEP4572582A1Display device and head-mounted display device including the same
Publication Date: 2025.06.18 SAMSUNG DISPLAY CO LTD
  • EP4572582A1 patent drawingFigure 1
  • EP4572582A1 patent drawingFigure 2
  • EP4572582A1 patent drawingFigure 3

AI summary

A display device and head-mounted display device including the same are provided. The display device includes a first monocrystalline semiconductor substrate (110) where first transistors (PTR1) are located, and a second monocrystalline semiconductor substrate (210) where second transistors (PTR2) are located, having a planar area that is greater than a planar area of the first monocrystalline semiconductor substrate (110), located above the first monocrystalline semiconductor substrate, including a display area (DAA) where subpixels (SP1 - SP3) including light-emitting elements (IL) are located, defining first through holes (TSV1) in which first conductive vias (RVA1) that are electrically connected to data lines (DL), which are connected to the subpixels, are located, and defining second through holes (TSV2) in which second conductive vias (RVA2) that are electrically connected to a gate-driving part (610, 620), which is electrically connected to the subpixels (SP1 - SP3), are located.