3D HNOR Memory Fabrication via Protective Layer Crystallization
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Solution Overview
Problem
Current fabrication processes for 3-dimensional arrays of NOR-type memory strings face challenges in achieving high charge carrier mobility and conductivity, which are crucial for efficient memory operations.
Innovation Solution
The process involves forming active stacks with channel regions protected by a protective layer, followed by crystallization of silicon materials with SiGe, which induces greater grain boundaries, enhancing charge carrier mobility and conductivity. This includes multiple trench-forming steps, deposition of channel and protective materials, and filling with conductive materials to create local word lines connected to decoding circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for 3D NOR memory strings, then manufacturing simplicity is maintained, but charge carrier mobility and conductivity are insufficient
Solution Approach 1:
A protective layer is deposited over the channel region before charge-trapping material deposition. This preliminary protective action prevents charge-trapping material from contaminating the channel region during subsequent processing steps, enabling the use of materials that would otherwise be incompatible with direct channel exposure while maintaining high charge carrier mobility.
Solution Approach 2:
The protective layer is applied specifically to the channel region, providing localized protection where it is most needed. This allows different regions of the structure to have different properties: the channel region maintains high purity and mobility while other regions can accommodate charge-trapping material deposition and processing.
2Reliability
If protective layer is deposited over channel region, then charge carrier mobility is improved through grain boundary enhancement, but manufacturing steps increase
Solution Approach 1:
The protective layer serves multiple functions simultaneously: it protects the channel region from charge-trapping material contamination, provides a platform for controlled deposition, and enables grain boundary formation through crystallization. By merging these functions into a single layer, the patent reduces overall device complexity despite adding a fabrication step.
Solution Approach 2:
The protective layer is formed using composite material deposition and crystallization processes that create grain boundaries within the layer structure. This composite approach, combining amorphous deposition with crystalline formation, enhances charge carrier mobility while integrating seamlessly with existing fabrication workflows.
3Reliability
If amorphous silicon and protective material are deposited then crystallized in anneal step, then charge carrier mobility and current density are enhanced, but processing temperature requirements increase
Solution Approach 1:
The patent employs parameter changes in the annealing process, optimizing temperature, time, and atmospheric conditions to achieve crystallization of the amorphous silicon and protective material. By carefully controlling these parameters, the process achieves grain boundary formation and phase transformation at temperatures that enhance charge carrier mobility without causing damage to other structure components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in highly efficient HNOR arrays with improved charge carrier mobility, conductivity, and current densities, enabling better performance in memory operations.
Implementation Method 1
Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step
Implementation Method 2
Both the silicon for the channel regions and the protective material may be deposited in amorphous form
Implementation Method 3
Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step
Data Source
AI summary
In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.