Horizontal Nanosheet FETs with Crystalline Barrier Layers
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Solution Overview
Problem
Horizontal nanosheet FETs with InGaAs channels face significant scaling limitations due to high band-to-band tunneling leakage and parasitic bipolar effects, making them unusable for mobile systems operating at supply voltages above 0.75V, and there is a tradeoff between reducing leakage and increasing parasitic resistance by adjusting the effective channel length.
Innovation Solution
The implementation of a horizontal nanosheet FET design with crystalline barrier material layers at the extension regions of the source and drain electrodes, where the thickness is greater than at the channel region, and lightly doping the extension regions to increase electron mobility and reduce parasitic leakage without increasing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the effective channel length is increased to reduce band-to-band tunneling leakage, then BTBT leakage is reduced, but parasitic resistance increases
Solution Approach 1:
The patent applies local quality by implementing a non-uniform doping profile where the extension regions have different doping concentrations than the channel region. Specifically, the extension regions are lightly doped (1e17 to 1e19 atoms/cm³) while the channel region maintains higher doping, creating localized electrical properties that reduce BTBT leakage at the extension regions without compromising overall device performance
Solution Approach 2:
The patent extends the effective channel length beyond the gate length by creating extension regions that protrude under the spacers. This dimensional extension in the lateral direction increases the effective channel length (Leff > LG), reducing band curvature and BTBT leakage without requiring an increase in gate length, thus avoiding the associated parasitic resistance penalty
2Object-generated harmful factors
If the effective channel length is increased to reduce parasitic bipolar effect, then PBE gain is reduced, but parasitic resistance increases
Solution Approach 1:
The patent applies local quality by implementing a non-uniform doping profile where the extension regions have different doping concentrations than the channel region. Specifically, the extension regions are lightly doped (1e17 to 1e19 atoms/cm³) while the channel region maintains higher doping, creating localized electrical properties that reduce BTBT leakage at the extension regions without compromising overall device performance
Solution Approach 2:
The patent extends the effective channel length beyond the gate length by creating extension regions that protrude under the spacers. This dimensional extension in the lateral direction increases the effective channel length (Leff > LG), reducing band curvature and BTBT leakage without requiring an increase in gate length, thus avoiding the associated parasitic resistance penalty
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces band-to-band tunneling and parasitic bipolar effects, achieving a 10 times reduction in overall parasitic leakage while maintaining comparable parasitic resistance, enhancing carrier mobility and operational voltage capabilities.
Implementation Method 1
A consequence of this small direct bandgap is a large amount of band-to-band tunneling (BTBT) leakage current
Implementation Method 2
lightly doping the extension regions to increase electron mobility and reduce parasitic leakage without increasing parasitic resistance
Data Source
AI summary
A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.