hNSFET Gate Isolation Layout for Dense Fin Active Regions
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Solution Overview
Problem
As integrated circuit devices shrink, increasing integration density of field-effect transistors poses challenges in maintaining performance and reliability, particularly in the design and manufacturing of horizontal nanosheet field-effect transistors (hNSFETs) due to complexities in fin active regions, gate cut insulating patterns, and inter-region insulating patterns.
Innovation Solution
The integrated circuit device incorporates a substrate with fin active regions, isolation films, gate lines, and inter-region insulating patterns, where the inter-region insulating pattern partially penetrates the gate line in a vertical direction, with specific surface and side wall configurations to enhance transistor performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of integrated circuit device is decreased to increase integration density, then the number of transistors per unit area increases, but manufacturing defects and reliability issues increase
Solution Approach 1:
The device is segmented into separate NMOS and PMOS transistor regions with distinct fin active regions, gate lines, and isolation structures. This segmentation allows independent optimization of each transistor type while maintaining high integration density through systematic arrangement of multiple nanosheet stacks within each region.
Solution Approach 2:
Different regions of the substrate are assigned different properties: NMOS transistor region with n-type doped fins, PMOS transistor region with p-type doped fins, and intermediate regions with specific insulating patterns. Each region is locally optimized for its specific function while contributing to overall high-density integration.
2Quantity of substance
If fin active regions are closely spaced to increase integration density, then more transistors fit on substrate, but electrical interference and manufacturing precision requirements increase
Solution Approach 1:
Inter-region insulating patterns are introduced as intermediary structures between adjacent fin active regions and between NMOS and PMOS regions. These insulating patterns act as buffers that reduce electrical interference and provide manufacturing tolerance, allowing closely spaced fins while maintaining signal integrity and reducing cross-talk.
Solution Approach 2:
Isolation films and insulating patterns are strategically placed to create equipotential regions between adjacent fins, preventing electrical interference while maintaining minimal spacing. This allows maximum density without compromising manufacturing precision requirements.
3Ease of manufacture
If gate lines extend continuously across device regions to simplify manufacturing, then fabrication process is easier, but electrical isolation between NMOS and PMOS regions becomes difficult
Solution Approach 1:
Gate lines are segmented into separate NMOS gate lines and PMOS gate lines that do not directly connect, with insulating patterns positioned between them. This segmentation maintains electrical isolation between complementary transistor regions while allowing each gate line to be fabricated using similar processes, balancing manufacturing simplicity with electrical isolation requirements.
Solution Approach 2:
Inter-region insulating patterns serve as intermediaries between NMOS and PMOS gate lines, preventing direct electrical connection while maintaining physical proximity for compact layout. These insulating structures enable continuous gate line fabrication processes while ensuring proper electrical isolation.
Data Source
AI summary
An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.