Hold Slack Optimization in Synchronous Logic Networks
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Solution Overview
Problem
In circuit design, identifying the optimal location to insert delay cells to address hold race violations while maintaining setup requirements and minimizing power consumption is challenging, as excessive delay cells can lead to functional failures and increased power usage.
Innovation Solution
A method and apparatus that modify synchronous logic networks to ensure hold slack at all pins is greater than or equal to a user-specified threshold, while preventing setup slack from becoming negative, by calculating and inserting delay cells at specific points identified through static timing analysis and congestion calculations, thereby optimizing delay, power, and electrical robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay cells are inserted to address hold race violations, then hold slack is improved, but setup slack may become negative and power consumption increases
Solution Approach 1:
The patent applies local quality by calculating and inserting delay cells only at specific locations where hold slack is deficient, rather than uniformly throughout the logic network. The method identifies critical paths using congestion calculations and places delay cells strategically at pins with negative hold slack, thereby improving hold timing only where needed while minimizing overall power consumption and avoiding setup time violations.
2Reliability
If delay cells are inserted to address hold race violations, then hold slack is improved, but setup requirements may be violated
Solution Approach 1:
The patent employs feedback through iterative timing analysis. After inserting delay cells at recommended locations, the method performs another round of timing analysis to recalculate hold and setup slack values. This feedback loop allows the system to verify that the inserted delay cells have improved hold slack while maintaining setup timing requirements, and to adjust the solution if necessary.
3Reliability
If multiple delay cells are inserted to fix hold failures, then hold analysis is improved, but the number of logic cells increases
Solution Approach 1:
The patent applies partial action by inserting delay cells only at the minimum necessary locations to resolve hold violations. The method calculates congestion values and identifies the most critical paths, placing delay cells selectively rather than exhaustively. This partial approach achieves sufficient hold slack improvement while avoiding the excessive insertion of delay cells that would increase device complexity.
Data Source
AI summary
A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.