Hold-Time Violation Fixing via Net Ordering and Buffer Allocation
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Solution Overview
Problem
In semiconductor chip design, hold-time violations occur due to the complex placement and routing of macrocells and regular logic, making it difficult to introduce buffers for signal timing corrections, as the chip real estate is already consumed by these components, and wiring channels may be utilized, rendering wiring solutions impractical.
Innovation Solution
The approach involves early analysis and allocation of placement regions for hold-time fixing, using ideal clocks to determine clock tree structure constraints, and ordering wiring nets to delay those with hold-time violations, thereby eliminating the need for hold buffers by wiring them later in the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffers are introduced for hold-time fixing, then hold-time violations are corrected, but chip real estate is consumed and wiring channels are utilized
Solution Approach 1:
The patent applies preliminary action by allocating placement regions for hold-time fixing buffers before the main placement process. This early reservation of space ensures that buffers can be inserted without consuming additional chip real estate, as the area is pre-designated during the placement planning phase
Solution Approach 2:
The patent extracts the hold-time fixing function into a separate, dedicated placement region that is isolated from the main macrocell placement area. This separation allows buffers to be placed in predetermined zones without interfering with the placement of functional blocks, effectively removing the conflict between buffer placement and chip real estate constraints
2Reliability
If buffers are introduced for hold-time fixing, then hold-time violations are corrected, but device complexity increases
Solution Approach 1:
The patent segments the placement process into distinct phases: initial macrocell placement, hold-time analysis, and buffer placement in allocated regions. This segmentation simplifies the overall device complexity by breaking down the complex task of hold-time fixing into manageable, sequential steps with clear boundaries
Solution Approach 2:
The patent introduces an intermediary placement region that serves as a mediator between macrocell placement and buffer placement. This intermediary zone allows the placement tool to insert buffers without disrupting the existing macrocell arrangement, reducing the complexity of re-optimizing the entire placement
3Productivity
If wiring is performed early, then routing is completed sooner, but hold-time violations cannot be addressed
Solution Approach 1:
The patent performs preliminary actions by allocating placement regions and performing hold-time analysis before detailed routing begins. This early assessment identifies which nets require hold-time fixing, allowing the routing process to be optimized subsequently without delaying overall productivity
Solution Approach 2:
The patent introduces dynamic ordering of net routing based on hold-time violation status. Nets identified as having hold-time violations are routed later after buffers are placed, while non-violating nets are routed earlier. This dynamic approach maintains high productivity by keeping the routing pipeline active while ensuring reliability through targeted late routing of critical nets
Data Source
AI summary
Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete.