Cache Memory Partial-Write Pipeline With Holding Buffer and ECC
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Solution Overview
Problem
Existing memory systems face inefficiencies in managing partial write requests, leading to increased processing time and power consumption due to the need for read-modify-write (RMW) operations, which are not optimized in current hierarchical cache memory architectures.
Innovation Solution
A processor system with a cache memory pipeline that includes a holding buffer, an anchor stage, and an RMW pipeline to manage partial writes by merging data payloads with conforming data, generating ECC syndromes, and writing the merged data with updated ECCs, optimizing RMW operations to reduce processing cycles and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read-modify-write operations are performed in hierarchical cache memory, then data integrity is maintained through ECC syndromes, but processing time and power consumption increase
Solution Approach 1:
The patent performs preliminary actions by pre-fetching conforming data into the holding buffer before the RMW operation is needed. The anchor stage identifies partial writes in advance and prepares the conforming data from the cache line, so that when the RMW operation occurs, the data is already ready for merging, reducing processing time
Solution Approach 2:
The patent segments the RMW operation into distinct pipeline stages: the anchor stage identifies partial writes, the holding buffer stores conforming data, the merge stage combines data payloads with conforming data, and the syndrome generation stage creates ECC syndromes. This segmentation allows parallel processing and optimizes the overall operation
2Reliability
If read-modify-write operations are performed in hierarchical cache memory, then data integrity is maintained through ECC syndromes, but power consumption increases
Solution Approach 1:
The holding buffer pre-stores conforming data from the cache line before the RMW operation. By having this data ready in advance, the system avoids additional memory access cycles that would consume extra power, while still maintaining data integrity through the merge stage and ECC syndrome generation
3Device complexity
If partial write requests are processed using traditional memory systems, then simplicity is maintained, but processing efficiency decreases
Solution Approach 1:
The patent embeds a specialized RMW pipeline within the existing hierarchical cache memory structure. The holding buffer, anchor stage, and merge stage are nested components that work together to handle partial writes efficiently without requiring a complete redesign of the memory system, thus maintaining relative simplicity while improving productivity
Data Source
AI summary
Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI.