Holding Registers for Concurrent Register Access

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Solution Overview

Problem

Current semaphore mechanisms limit performance by controlling simultaneous access to shared registers, leading to unnecessary overhead and reduced concurrency, especially in multi-threading and virtualization environments where multiple sources access wider registers.

Innovation Solution

Implementing N holding registers with source identifiers in each slave engine to allow multiple sources to access different target registers simultaneously without using semaphores, enabling parallel register transactions and independent software operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If semaphore mechanism is used to ensure atomicity for multiple sources accessing end registers, then reliability of register access is improved, but productivity is worsened due to overhead and limited concurrency

Engineering Contradiction:
Improveatomicity of register accessVSAvoidregister access throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The end register is segmented into multiple holding registers (one per source), allowing each source to update its own holding register independently. This eliminates the need for semaphores while ensuring atomicity, as each source only needs to update its dedicated holding register without blocking other sources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Holding registers are introduced as intermediary structures between sources and end registers. These holding registers buffer updates from multiple sources and facilitate atomic commits to the end register, eliminating the need for semaphore-based coordination while maintaining reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If semaphore is acquired before each register access to ensure atomicity, then reliability is improved, but loss of time is worsened due to overhead

Engineering Contradiction:
Improveatomicity of register accessVSAvoidoverhead per register access
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Each source is pre-assigned a dedicated holding register before access occurs. This preliminary arrangement eliminates the need for runtime semaphore acquisition and release operations, significantly reducing overhead time while maintaining atomicity through the holding register mechanism.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If two sources access different 64-bit registers simultaneously through semaphore mechanism, then reliability is maintained, but productivity is limited due to sequential access control

Engineering Contradiction:
Improveatomicity of register accessVSAvoidconcurrency of register access
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The register access space is segmented into multiple holding registers, one for each source. This allows Source 0 to update Holding Register 0 and Source 1 to update Holding Register 1 simultaneously without interference, enabling true parallel access while maintaining atomicity through the holding register architecture.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9542342B2Smart holding registers to enable multiple register accesses
Publication Date: 2017.01.10 MARVELL ASIA PTE LTD
  • US9542342B2 patent drawing
  • US9542342B2 patent drawing
  • US9542342B2 patent drawing

AI summary

A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2n, where n is the number of bits in the source identifier.