Processor Holding Stage Partial Instruction Execution

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Solution Overview

Problem

Processor pipelines face inefficiencies due to delays caused by pipeline hazards, which prevent instructions from reaching the execution stage in a timely manner, leading to diminished processing efficiency.

Innovation Solution

A processor system that partially or wholly executes stalled instructions in a holding stage with execution logic circuitry, allowing instructions to be processed before reaching the execution stage, thereby overcoming resource and data hazards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If instructions are delayed in the holding stage due to pipeline hazards, then resource availability is improved, but processing efficiency deteriorates

Engineering Contradiction:
Improveresource availabilityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by allowing the holding stage to perform execution operations on instructions before they are formally dispatched to the execution stage. This enables partial or complete execution of instructions while they are still held in the holding stage, so that when the instruction is eventually released to the execution stage, the actual execution work has already been completed or partially completed, thereby eliminating the efficiency loss from the delay.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The holding stage is given multi-functionality by enabling it to perform not only its traditional function of buffering instructions but also execution operations. The holding stage now serves dual purposes: it holds instructions waiting for hazard resolution and simultaneously executes operations on those instructions, thus improving resource utilization without adding separate execution hardware.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Loss of time

If instructions are held in the holding stage during hazards, then data gathering time is improved, but execution speed deteriorates

Engineering Contradiction:
Improvedata gathering timeVSAvoidexecution speed
Core Design Contradiction:
Loss of timeVSSpeed

Solution Approach 1:

The patent performs execution operations in advance during the holding stage while data is being gathered for hazard resolution. By executing operations before the instruction reaches the execution stage, the patent eliminates the speed penalty that would otherwise result from the delay caused by data gathering and hazard resolution.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the execution stage waits for stalled instructions, then resource hazards are avoided, but overall processing speed deteriorates

Engineering Contradiction:
Improveresource hazard avoidanceVSAvoidoverall processing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent executes instructions during the holding stage before they are released to the execution stage. This preliminary execution ensures that when the instruction is eventually released (after hazard resolution), the execution work has already been completed, so the execution stage does not need to wait, thereby maintaining high processing speed while still avoiding resource hazards through proper timing of the release.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuity of useful action by ensuring that execution operations continue to occur during the holding stage rather than stopping completely during hazard resolution. The execution logic in the holding stage keeps the pipeline productive during periods when instructions are stalled, preventing idle cycles in the execution stage.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8127114B2System and method for executing instructions prior to an execution stage in a processor
Publication Date: 2012.02.28 QUALCOMM INC
  • US8127114B2 patent drawing
  • US8127114B2 patent drawing
  • US8127114B2 patent drawing

AI summary

A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to the execution stage within the processor. Partially or wholly executing the instruction prior to the execution stage in the pipeline speeds up the execution of the instruction and allows the processor to more effectively utilize its resources, thus increasing the processor's efficiency.