Holding-Unit Logic Circuit for Low-Power Product-Sum Operation
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Solution Overview
Problem
Artificial neural networks face challenges with high power consumption and heat generation due to the increasing number of circuits, which affects the performance and reliability of semiconductor devices, especially in hierarchical architectures.
Innovation Solution
A semiconductor device is designed with a hierarchical artificial neural network architecture that includes specific transistor and logic circuit configurations, utilizing metal oxide transistors and capacitors to manage power consumption and thermal effects, featuring inverted signal outputs and adjustable resistance elements for efficient signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of circuits corresponding to neurons and synapses increases to enhance the scale of the artificial neural network, then the calculation capability and processing power are improved, but the power consumption and heat generation increase significantly
Solution Approach 1:
The patent divides the artificial neural network into multiple layers (first layer with first neurons, second layer with second neurons, etc.) and implements hierarchical processing. Each layer processes signals independently before passing them to the next layer, which segments the overall computation into manageable stages. This segmentation allows for better power management and heat dissipation while maintaining high calculation capability through parallel processing across layers.
Solution Approach 2:
The patent transitions from a single-layer neural network to a multi-layer hierarchical architecture, adding the dimension of depth to the network structure. By organizing neurons into multiple layers with different functions (e.g., input layer, hidden layers, output layer), the system achieves enhanced computational power without proportionally increasing power consumption, as each layer can be optimized independently for energy efficiency.
2Productivity
If the number of circuits corresponding to neurons and synapses increases to enhance the scale of the artificial neural network, then the calculation capability is improved, but the heat generation increases and affects circuit component characteristics
Solution Approach 1:
By segmenting the neural network into multiple hierarchical layers, the patent distributes heat generation across different spatial zones rather than concentrating it in a single dense circuit block. Each layer can be thermally managed independently, allowing for better heat dissipation strategies and reducing the overall thermal impact on circuit component characteristics while maintaining high calculation capability.
Solution Approach 2:
The patent applies different design optimizations to different layers of the neural network, allowing each layer to have tailored characteristics suited to its specific computational requirements and thermal environment. This local optimization enables certain layers to be designed with enhanced thermal management features while others focus on computational efficiency, thereby managing heat generation effectively across the entire system.
3Power
If the number of circuits corresponding to neurons and synapses increases to enhance the scale of the artificial neural network, then the processing power is improved, but the power consumption increases
Solution Approach 1:
The patent segments the neural network processing into multiple hierarchical layers, where each layer performs specific computational tasks. This segmentation enables selective activation of layers based on processing requirements, allowing the system to maintain high processing power when needed while consuming less power during simpler operations. The hierarchical structure facilitates efficient power management by enabling partial processing rather than always engaging the full network capacity.
Solution Approach 2:
The patent implements dynamic control mechanisms that allow the neural network to adjust its operational state based on computational demands. Layers can be dynamically activated or deactivated, and signal transmission between layers can be modulated, enabling the system to optimize the balance between processing power and power consumption in real-time according to the specific task requirements.
Data Source
AI summary
A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.