Hollow Channel 3D Memory Device with SiGe Material
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Solution Overview
Problem
Conventional 3D semiconductor memory devices with vertical channels face issues of low carrier mobility due to polysilicon channel material, leading to small on-state channel current, reliability concerns, and increased manufacturing complexity and cost.
Innovation Solution
The technology introduces a vertical channel-type 3D semiconductor memory device with hollow channels formed by controlling deposition time and reducing etching angle, which decreases channel stress and defect density, enhancing carrier mobility and manufacturing ease.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon channel material is used in vertical channel-type 3D semiconductor memory devices, then manufacturing is simplified, but carrier mobility decreases leading to low on-state channel current
Solution Approach 1:
The patent changes the physical and chemical parameters of the channel material from conventional polysilicon to silicon germanium (SiGe) with specific germanium content (10-50 at%). This parameter change increases carrier mobility by reducing effective mass and enhancing hole transport, while maintaining compatibility with existing manufacturing processes. The SiGe material system allows continuous tuning of parameters to optimize both mobility and manufacturability.
Solution Approach 2:
The patent employs composite material structure by forming a gradient SiGe channel where the germanium concentration varies through the channel thickness. The channel includes a SiGe layer with higher Ge content at certain regions and lower Ge content at other regions, creating a composite structure that optimizes carrier mobility while managing stress and manufacturing complexity. This composite approach resolves the contradiction by combining benefits of different material compositions.
2Quantity of substance
If memory cells are stacked along vertical direction to increase storage density, then storage capacity increases, but channel thickness variation occurs due to etching process limitations
Solution Approach 1:
The patent addresses channel thickness variation by changing the etching process parameters to achieve a controlled etching angle between 80-85 degrees. This parameter optimization, combined with selective removal of sacrificial layers, compensates for the natural tapering effect and achieves uniform channel thickness across vertically stacked cells, maintaining manufacturing precision while enabling high storage density.
Solution Approach 2:
The patent employs preliminary action by forming sacrificial layers (first and second sacrificial layers) before defining the final channel structure. These preliminary structures are strategically positioned and selectively removed to compensate for etching angle limitations, pre-correcting the channel thickness uniformity issue before the main channel formation process occurs.
3Ease of manufacture
If conventional etching processes are used for deep hole formation, then manufacturing is straightforward, but channel thickness varies between upper and lower memory cells
Solution Approach 1:
The patent optimizes the etching process by precisely controlling the etching angle parameter to fall within 80-85 degrees. This parameter change, combined with adjusted etching chemistry and process conditions, achieves deep hole formation with improved wall angle control, thereby maintaining ease of manufacture while significantly improving channel thickness consistency across vertically stacked memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the consistency and reliability of storage performance by achieving uniform channel thickness and reduced defect density, simplifying the manufacturing process and reducing costs.
Implementation Method 1
depositing a barrier layer, a storage layer, and a tunnel layer in sequence on an inner wall of one of the plurality of through-holes
Implementation Method 2
depositing a channel material on a surface of the tunnel layer of one of the plurality of gate stacks
Data Source
AI summary
A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing alternating insulating and electrode layers on a substrate to form a multi-layer film. The method further includes etching the film to the substrate to form through-holes, each of which defines a channel region. The method further includes depositing barrier, storage, and tunnel layers in sequence on inner walls of through-holes to form gate stacks. The method further includes depositing and incompletely filling a channel material on a surface of the tunnel layer of gate stacks to form a hollow channels. The method further includes forming drains in contact hole regions for bit-line connection in top portions of the hollow channels. The method further includes forming sources in contact regions between the through-holes and the substrate in bottom portions of the hollow channels.