Hollow U-Shaped MIM Capacitor Structure for Higher Memory Capacitance
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Solution Overview
Problem
The limited effective area of the lower electrode in metal-insulator-metal (MIM) structures within memory devices restricts memory capacitance, leading to reduced performance as memory devices become smaller.
Innovation Solution
A semiconductor device is fabricated with a hollow U-shaped base capacitor, featuring a conductive pattern extending vertically from a substrate, a support structure, and a dielectric layer covering a first conductive layer, which serves as a lower electrode, enhancing the effective area and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional MIM capacitor structure is used, then the device structure is simple, but the effective area of the lower electrode is limited
Solution Approach 1:
The patent implements a hollow U-shaped lower electrode structure where an inner conductive pattern is nested within an outer conductive pattern. This nesting approach allows the lower electrode to have both a top surface area and a sidewall area, effectively increasing the total effective area without proportionally increasing the footprint area. The inner electrode is positioned inside the outer electrode's hollow region, creating a nested configuration that maximizes capacitance within the available space.
Solution Approach 2:
The patent transitions from a planar lower electrode to a three-dimensional hollow U-shaped structure. By adding vertical sidewalls and creating a hollow interior, the electrode utilizes the third dimension (height/depth) to increase its effective area. The sidewalls of the hollow structure provide additional surface area for capacitance formation, moving beyond the two-dimensional planar limitation of conventional MIM capacitors.
2Quantity of substance
If the lower electrode area is increased to improve capacitance, then memory capacitance increases, but the memory device size increases
Solution Approach 1:
The hollow U-shaped lower electrode with nested inner and outer patterns allows increased effective area within a compact footprint. The inner electrode fits within the hollow region of the outer electrode, enabling both electrodes to contribute to capacitance without requiring proportional increases in the overall device volume.
Solution Approach 2:
By creating vertical sidewalls and a hollow three-dimensional structure, the patent increases the effective electrode area in the vertical dimension rather than expanding the horizontal footprint. This allows capacitance to be increased while maintaining a compact planar footprint, as the additional capacitance comes from the sidewall surfaces of the hollow structure.
3Area of moving object
If a hollow U-shaped base structure is formed, then the effective area of the lower electrode is expanded, but the fabrication process complexity increases
Solution Approach 1:
The patent employs preliminary sacrificial layers (first and second sacrifice layers) that are formed before the final electrode structure. These sacrificial layers are used to define the hollow U-shaped region and are subsequently removed to create the desired hollow structure. This preliminary action simplifies the overall fabrication by using temporary structures that guide the formation of the complex hollow geometry.
Solution Approach 2:
The sacrificial layers serve as intermediary structures during fabrication. They are introduced to enable the formation of the hollow U-shaped base and are later removed after serving their purpose. These intermediary layers make the fabrication of the complex hollow structure more manageable by providing temporary support and definition during the manufacturing process.
Data Source
AI summary
A method for fabricating a semiconductor device, including the steps of: providing a substrate having an etch stop layer formed thereon; forming a preliminary stacked structure on the etch stop layer, the preliminary stacked structure including a lower sacrifice layer contacting the etch stop layer, a support layer, and an upper sacrifice layer; forming a hole penetrating the preliminary stacked structure and the etch stop layer; forming a conductive pattern in the hole; removing the upper sacrifice layer and a portion of the support layer; removing the lower sacrifice layer; forming a first conductive layer covering the conductive pattern; and forming a dielectric layer covering the first conductive layer, a remaining portion of the support layer, and the etch stop layer.