Hollow Pillar Gate Nonvolatile Memory Transistor Parasitic Capacitance

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Solution Overview

Problem

The existing nonvolatile semiconductor memory transistors face challenges in increasing the capacitance between the floating gate and the control gate while minimizing parasitic capacitance between the control gate and the island-shaped semiconductor, which affects the operating speed and efficiency of data writing and erasing.

Innovation Solution

A nonvolatile semiconductor memory transistor design featuring an island-shaped semiconductor with a hollow pillar-shaped floating gate and control gate, where a tunnel insulating film is interposed between the floating gate and the channel region, and an inter-polysilicon insulating film is used between the control gate and the floating gate, reducing parasitic capacitance by ensuring the control gate and island-shaped semiconductor are not in close proximity with an insulating film in between.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the control gate is brought into close proximity with the island-shaped semiconductor to increase capacitance, then the capacitance between floating gate and control gate increases, but parasitic capacitance between control gate and island-shaped semiconductor increases reducing operating speed

Engineering Contradiction:

Improvecapacitance between floating gate and control gateVSAvoidoperating speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

An insulating film is introduced as an intermediary between the control gate and the island-shaped semiconductor. This insulating film acts as a mediator that prevents direct electrical interaction, thereby eliminating parasitic capacitance while allowing the control gate to maintain close proximity to the floating gate for high capacitance coupling.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The space between the control gate and island-shaped semiconductor is segmented by introducing an insulating film layer. This segmentation separates the electrical fields, preventing unwanted capacitance formation while maintaining the structural proximity needed for effective control gate coupling with the floating gate.

Inventive Principle:

Principle #1Segmentation

2Reliability

If the control gate covers the upper and lower surfaces of the floating gate to increase capacitance, then writing and erasing are facilitated, but parasitic capacitance with the island-shaped semiconductor is generated

Engineering Contradiction:

Improvewriting and erasing efficiencyVSAvoidparasitic capacitance

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The insulating film serves as a mediator that allows the control gate to cover the floating gate surfaces for effective coupling while preventing harmful parasitic capacitance generation with the island-shaped semiconductor below.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating film is selectively placed in specific locations where parasitic capacitance would form between the control gate and island-shaped semiconductor, while allowing direct coupling in regions where capacitance between control gate and floating gate is needed for writing and erasing operations.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the capacitance between the floating gate and the control gate, improving the efficiency of data writing and erasing operations by reducing parasitic capacitance, thereby facilitating more reliable and efficient data storage.

Implementation Method 1

a tunnel insulating film is interposed between the floating gate and the channel region

Methodology Applied

Scientific EffectQuantum tunneling:

Implementation Method 2

an inter-polysilicon insulating film is used between the control gate and the floating gate, reducing parasitic capacitance

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8772863B2Nonvolatile semiconductor memory transistor, nonvolatile semiconductor memory, and method for manufacturing nonvolatile semiconductor memory

Publication Date: 2014.07.08 UNISANTIS ELECTRONICS SINGAPORE PTE LTD

AI summary

A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped charge storage layer arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the charge storage layer and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the charge storage layer in such a manner that an insulating film is interposed between the control gate and the charge storage layer. The insulating film is arranged so as to be interposed between the charge storage layer and the upper, lower, and inner side surfaces of the control gate.