Hollow Conductive Vias for Embedded Semiconductor Chip Thermal Stress
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Solution Overview
Problem
The existing semiconductor packaging techniques face issues with thermal stress due to mismatched coefficients of thermal expansion (CTE) of components surrounding conductive vias, leading to separation of the circuit structure from semiconductor chip electrode pads, especially at high frequencies, and fail to meet the demand for fine pitch and reliable signal transmission.
Innovation Solution
A circuit board structure with semiconductor chips is designed to include a supporting board with cavities, embedded semiconductor chips, a protection layer, a metal layer, a dielectric layer, and hollow conductive vias that match the CTE of surrounding materials, reducing thermal stress and ensuring reliable electrical connections through the use of hollow conductive vias and fully-plated metal vias for stacked structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor packaging techniques are used with wire bonding or flip chip processes, then the number of I/O connection terminals can be increased, but the conductive connection route becomes too long, causing signal loss and distortion at high frequencies
Solution Approach 1:
The patent transitions from planar surface mounting to three-dimensional embedding of semiconductor chips within the package substrate. By creating cavities and embedding chips vertically within the substrate thickness, the invention achieves shorter conductive paths while maintaining high I/O density, effectively resolving the contradiction between terminal quantity and signal quality.
2Reliability
If multiple connecting interface processes are performed for wire bonding or flip chip packaging, then electrical connections can be established, but the manufacturing process becomes complicated
Solution Approach 1:
The patent combines multiple separate manufacturing steps into an integrated embedded chip process. Instead of separate wire bonding or flip chip attachment steps, the invention embeds chips directly into cavities within the substrate during the substrate fabrication process itself, reducing process complexity while maintaining connection reliability.
3Reliability
If conductive vias are formed in the package substrate to connect circuitry, then electrical connections are established, but mismatched coefficients of thermal expansion cause thermal stress and separation of the circuit structure from electrode pads
Solution Approach 1:
The patent applies different material properties to different regions of the package substrate. Specifically, hollow conductive vias are used in regions requiring thermal expansion accommodation, while solid via structures are used in other regions. This localized material selection optimizes both electrical connection reliability and thermal stress resistance.
Solution Approach 2:
The patent employs composite via structures combining hollow and solid configurations, and uses multiple material layers including dielectric materials with matched thermal expansion coefficients. This composite approach allows the structure to accommodate thermal stress while maintaining reliable electrical connections.
4Ease of manufacture
If the package substrate uses conventional conductive via structures, then manufacturing is simplified, but thermal stress from mismatched CTE causes separation of circuit structure from electrode pads
Solution Approach 1:
The patent modifies the physical parameters of conductive vias by creating hollow structures instead of solid fills. This parameter change allows the via structure to accommodate thermal expansion differences while maintaining manufacturing feasibility through standard via formation processes followed by selective filling or leaving hollow.
Data Source
AI summary
A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.