Homogeneous Chiplet Stacking for Low-Latency Memory Access
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Solution Overview
Problem
Traditional computing systems on silicon dies face challenges due to power versus performance tradeoffs and design and semiconductor technology constraints, leading to high design costs and poor performance.
Innovation Solution
A homogeneous chiplet system is introduced, comprising vertically stacked or horizontally coupled chiplets with on-die interconnect structures and vertical die-to-die interconnection structures, allowing for efficient data signal transfer and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional silicon dies are stacked on top of each other or coupled via interposers, then three-dimensional integration is achieved, but design costs increase and performance deteriorates
Solution Approach 1:
The system divides the computing system into multiple homogeneous chiplet modules, each containing logic blocks and memory blocks. These modular chiplets can be independently designed, manufactured, and tested, reducing overall design complexity while enabling three-dimensional stacking integration.
Solution Approach 2:
The patent employs homogeneous chiplets that can serve multiple functions - each chiplet contains both logic blocks and memory blocks that can be configured in different arrangements (2D or 3D stacking) to meet various computational and storage requirements, reducing the need for specialized components.
2Speed
If data is transferred between logic blocks and memory blocks on the same die, then transfer speed is fast, but latency increases for cross-die communication
Solution Approach 1:
The patent implements vertical stacking of chiplets in the third dimension, allowing logic blocks on one chiplet to directly access memory blocks on an adjacent chiplet through vertical interconnects. This 3D arrangement reduces the physical distance and number of interconnection layers compared to traditional 2D planar layouts, decreasing latency while maintaining high transfer speeds.
Solution Approach 2:
The patent introduces specialized interconnect structures and interface circuits that mediate between logic blocks and memory blocks across different chiplets. These intermediary components optimize data transfer by providing direct vertical pathways and reducing protocol overhead, thereby minimizing latency in cross-chiplet communication.
3Productivity
If homogeneous chiplets are vertically stacked, then bandwidth increases for data-intensive operations, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates alignment features, registration marks, and guide structures on each chiplet before stacking. These preliminary alignment mechanisms are built into the chiplet design, enabling precise positioning and reducing the difficulty of achieving required stacking alignment precision during assembly.
Solution Approach 2:
The patent employs advanced packaging techniques that control critical parameters such as bonding temperature, pressure, and timing during the stacking process. By precisely controlling these manufacturing parameters, the system achieves high stacking alignment precision and enables greater vertical integration to increase bandwidth for data-intensive operations.
Data Source
AI summary
Homogeneous chiplets configurable both as a two-dimensional system or a three-dimensional system are described. An example chiplet system has a first homogeneous chiplet (HC) including a first integrated circuit (IC) die having a first logic block and a first memory that are interconnected via a first path for transfer of data signals between the first logic block and the first memory block. A second HC including a second IC die having a second logic block and a second memory block, interconnected via a second path for transfer of data signals between the second logic block and the second memory block, is stacked vertically on top of the first HC to provide a third path for transfer of data signals between the first logic block and the second memory block and a fourth path for transfer of data signals between the second logic block and the first memory block.