Homogeneous Delay Line Layout Without Exit Tree Delay Penalty
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Solution Overview
Problem
Conventional variable delay circuits face issues with predictability, power consumption, layout area, and negative bias temperature instability due to complex exit tree circuitry, which increases forward path delay and susceptibility to degradation.
Innovation Solution
A delay-locked loop with a homogenous delay line circuit and integrated measurement initialization circuitry, using identical delay elements and eliminating exit tree circuitry to simplify the architecture, reduce power consumption, and enhance delay accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional exit tree circuitry is used to tap output signals, then signal routing flexibility is improved, but forward path delay increases and predictability decreases
Solution Approach 1:
The patent removes the complex exit tree circuitry from the delay line architecture. Instead of using multiple layers of circuit elements to tap outputs, the invention directly taps the output of individual delay elements, eliminating the additional delay introduced by exit tree logic while maintaining the ability to select different delay points.
Solution Approach 2:
The delay line is segmented into multiple identical delay elements, each capable of being independently selected as an output tap point. This segmentation allows flexible signal routing to different delay stages without requiring a complex exit tree structure, as each segment can be independently accessed.
2Adaptability or versatility
If different types of circuit elements are used in exit tree circuitry, then signal routing capability is improved, but delay predictability decreases
Solution Approach 1:
The patent employs homogenous delay elements throughout the delay line, where each element is identical in structure and characteristics. This uniformity ensures predictable and consistent delay values across all stages, eliminating the variability introduced by mixing different types of circuit elements in the exit tree.
3Ease of operation
If complex exit tree circuitry is implemented, then output signal access is improved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the power-consuming exit tree circuitry from the architecture. Output signals are accessed directly from delay element outputs without passing through additional logic layers, significantly reducing power consumption while maintaining ease of signal access.
4Adaptability or versatility
If exit tree circuitry is used, then signal distribution is improved, but susceptibility to NBTI degradation increases
Solution Approach 1:
The patent removes the exit tree circuitry that is particularly susceptible to NBTI degradation. By eliminating these vulnerable circuit elements, the system achieves comparable signal distribution functionality through direct tapping while significantly improving reliability and resistance to bias temperature instability.
5Adaptability or versatility
If exit tree circuitry is implemented, then signal routing is improved, but layout area increases
Solution Approach 1:
The patent extracts and eliminates the exit tree circuitry, which occupies significant layout area. The simplified architecture that directly taps delay element outputs requires minimal additional routing space, dramatically reducing the overall layout area while maintaining signal routing capability.
Data Source
AI summary
Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a delay length, and, in a second mode, to determine an initial delay. The apparatus further including a delay line circuit coupled to the controller and includes delay elements. Each of the delay elements includes delay gates that are the same type of delay gate. The delay line circuit is configured to, in the first mode propagate a signal through one or more of the delay elements to provide a delayed signal. The delay line circuit is further configured to, in the second mode, propagate a pulse signal through one or more of the delay elements and provide a corresponding output signal from each of the one or more delay elements responsive to the pulse signal reaching an output of the corresponding delay element.