Hopping Bus Architecture for SoC Data Transfer
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Solution Overview
Problem
Advanced silicon manufacturing processes lead to complex SoC architectures with limited data transfer speeds and difficulty in setting clock frequencies due to large mesh networks and shared clock signals, making it challenging to increase clock frequency without affecting PVT variations.
Innovation Solution
The introduction of hopping bus (HB) architectures with intra-chip and inter-chip adaptors that convert information between different protocols, allowing for efficient transfer of data and interrupts over a single HB protocol, independent of clock signals, and enabling high-speed, pseudo-synchronous data transfer between modules and SoCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If AXI-based mesh architecture is used to connect processor modules and interface controllers, then information transfer capability is provided, but data transfer speed is limited and device complexity increases
Solution Approach 1:
The patent segments the monolithic AXI mesh architecture into modular hopping bus components. Each module (processor or interface controller) becomes an independent node that can hop between modules through standardized interfaces, replacing the complex centralized mesh control with distributed modular units that simplify the overall system architecture while maintaining transfer capability
Solution Approach 2:
The patent introduces a clock signal as an intermediary that synchronizes operations across modules. This shared clock acts as a mediator that coordinates data transfer timing between processor modules and interface controllers, enabling reliable communication without requiring complex mesh routing protocols or additional synchronization mechanisms
2Reliability
If shared clock signal is used to synchronize operations, then coordination between modules is achieved, but clock frequency cannot be increased due to PVT variations
Solution Approach 1:
The patent makes the clock signal dynamic by allowing modules to operate at different clock frequencies independently. Each module can adjust its local clock frequency to match its performance requirements and PVT conditions, while still maintaining coordination through the hopping bus protocol. This dynamic frequency adjustment capability enables higher speeds without sacrificing reliability
Solution Approach 2:
The patent changes the clock frequency parameter from a fixed system-wide value to a variable parameter that can be adjusted at each module level. By allowing individual modules to operate at optimized frequencies rather than being constrained by a single shared clock, the system can achieve higher overall performance while maintaining reliable coordination through protocol-level synchronization
3Productivity
If multiple channels and wires are provided for parallel transfer, then information transfer capability is enhanced, but manufacturing complexity and wire count increase significantly
Solution Approach 1:
The patent merges multiple separate AXI channels (read address, read data, write address, write data, buffer write response) into a single unified hopping bus interface. Instead of implementing separate physical channels for each function, the hopping bus protocol consolidates these operations into a single transfer mechanism that handles all channel functions sequentially, dramatically reducing the number of wires and routing complexity
Solution Approach 2:
The hopping bus interface provides universal functionality by handling multiple channel operations through a single standardized interface. The same physical interface and protocol can perform read operations, write operations, address transfers, and data transfers, making the system more manufacturable while maintaining full information transfer capability that would otherwise require multiple specialized channels
4Adaptability or versatility
If AXI bus interfaces with multiple channels are implemented, then data transfer functionality is provided, but number of wires and interconnections becomes very large
Solution Approach 1:
The patent extracts the essential function of data transfer from the complex AXI multi-channel interface and implements it through a simplified hopping bus mechanism. By taking out only the core data transfer capability and implementing it through sequential hopping transfers rather than parallel multi-channel architecture, the system maintains adaptability while significantly reducing the number of interconnections and wires required
Data Source
AI summary
A system-on-chip including non-hopping bus interfaces and a hopping bus. The non-hopping bus interfaces include a first non-hopping bus interface and a second non-hopping bus interface. The first non-hopping bus interface is configured to, based on a first protocol, receive information. The hopping bus includes intra-chip adaptors. The intra-chip adaptors are connected in series and respectively to the non-hopping bus interfaces. The intra-chip adaptors are configured to (i) according to a second protocol, convert the information into a first format for transmission over the hopping bus, and (ii) transfer the information in the first format over the hopping bus and between the intra-chip adaptors. The second protocol is different than the first protocol. The second non-hopping bus interface is configured to receive the information from the hopping bus based on the transmission of the information over the hopping bus.