Horizontal Avalanche Photodiode Stacked Chip Fill Factor
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Solution Overview
Problem
Conventional single-photon avalanche diode (SPAD) designs suffer from reduced fill factor on the imaging plane due to the area occupied by CMOS circuits, limiting the integration and miniaturization of photodetectors.
Innovation Solution
A stacked chip structure is implemented, where SPADs are on a top chip and support circuitry is on a separate bottom chip, enhancing the fill factor by separating the digital counters and CMOS circuitry, and using trenches and counter-doping techniques to manage the internal electric field and prevent unwanted breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS circuits are integrated on the same chip as SPADs, then device integration is improved, but fill factor is reduced
Solution Approach 1:
The device is segmented into two separate chips: a first chip containing the SPAD imaging array and a second chip containing the CMOS support circuitry. This segmentation allows each chip to be optimized for its specific function, with the SPAD chip achieving high fill factor and the CMOS chip providing full integration of support functions.
Solution Approach 2:
The solution transitions from a planar integration approach to a three-dimensional stacked architecture. By stacking the SPAD chip and CMOS chip vertically, the patent achieves both high fill factor on the SPAD chip and complete integration of support circuitry, effectively utilizing the vertical dimension to resolve the contradiction.
2Adaptability or versatility
If digital counters and CMOS circuitry are integrated on the same chip, then device integration is improved, but surface effects increase
Solution Approach 1:
By separating the SPAD photodetection functions on the first chip from the digital counters and CMOS circuitry on the second chip, the patent eliminates surface effects on the SPAD chip while maintaining full digital processing capability on the separate CMOS chip.
Solution Approach 2:
The harmful CMOS circuitry is extracted from the SPAD chip and placed on a separate second chip. This extraction removes the source of surface effects and unwanted breakdown from the sensitive photodetection region, while the extracted circuitry continues to provide necessary support functions.
3Speed
If p-n junction is reverse biased above breakdown voltage, then avalanche multiplication speed is improved, but unwanted breakdown increases
Solution Approach 1:
The CMOS circuitry that causes unwanted breakdown is extracted from the same chip as the SPADs and placed on a separate second chip. This physical separation eliminates the harmful electric fields and surface effects from the SPAD region, allowing the p-n junction to be reverse biased above breakdown voltage for fast avalanche multiplication without suffering from unwanted breakdown caused by adjacent CMOS circuits.
Solution Approach 2:
The patent introduces an intermediate structure (the stacked chip architecture with bonding interface) that allows the SPAD chip to operate at high reverse bias voltages for fast avalanche multiplication while the CMOS chip handles the digital processing. The bonding interface and separate chip structure act as intermediaries that prevent harmful interactions between the high-field SPAD region and the CMOS circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the fill factor of the SPAD imaging array, allowing for more efficient photon detection and reduced surface effects, thereby improving the performance and miniaturization of photodetectors.
Implementation Method 1
The SPAD regions have a p-n junction that is reverse biased above the breakdown voltage such that a single photo-generated carrier can trigger an avalanche multiplication process that causes current at the output of the photon detection cell to reach its final value quickly.
Implementation Method 2
A SPAD (also sometimes referred to as a Geiger-mode avalanche photodiode (G-APD)) is a solid-state photodetector capable of detecting a low intensity signal, such as low as a single photon.
Data Source
AI summary
An avalanche photodiode sensor includes a plurality of avalanche photodiodes disposed in a semiconductor material where individual avalanche photodiodes in the plurality of avalanche photodiodes have an internal electric field parallel with a first surface of the semiconductor material. The individual avalanche photodiodes in the plurality of avalanche photodiodes include a p-doped semiconductor region which extends into the semiconductor material, and an n-doped semiconductor region which extends into the semiconductor material. The internal electric field extends between the p-doped semiconductor region and the n-doped semiconductor region. Processing methods as examples are also proposed.