Horizontal Capacitor Layout for Uniform IC Capacitance
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Solution Overview
Problem
Existing capacitor designs in integrated circuits face challenges in achieving uniform capacitance due to uneven insulating layers, leading to excessive capacitance variation, which can be mitigated by using a horizontally-oriented capacitor with a thin insulating layer to maintain small IC chip sizes while ensuring uniform capacitance.
Innovation Solution
A method for fabricating a semiconductor device that includes forming a dummy structure over a substrate, creating spacers, and using a continuous poly on oxide definition edge (CPODE) pattern to form a trench filled with dielectric material, allowing for the formation of a horizontally-oriented capacitor with conductive features from adjacent transistors, thereby achieving uniform capacitance and reduced area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-oriented capacitor structure is used, then capacitance value can be maintained, but area occupancy increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from a vertically-oriented capacitor structure to a horizontally-oriented capacitor structure. This dimensional change allows the capacitor to achieve the required capacitance value with reduced area occupancy by utilizing the lateral space between adjacent transistors rather than requiring vertical stacking that consumes additional area.
Solution Approach 2:
The patent merges the capacitor structure with the transistor layout by positioning the horizontally-oriented capacitor between adjacent transistors. This integration allows the capacitor to share space with existing transistor structures, thereby reducing overall area occupancy while maintaining the required capacitance value.
2Productivity
If design rules shrink, then device density increases, but capacitance values decrease and manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by creating a horizontally-oriented capacitor with specific local characteristics between adjacent transistors. The capacitor structure is tailored to the local space available, utilizing the region between transistors with dimensions and materials optimized for that specific location, thereby maintaining capacitance value despite overall design rule shrinkage.
Solution Approach 2:
The patent changes key parameters of the capacitor structure by transitioning from vertical to horizontal orientation and adjusting the dielectric layer thickness and material composition. These parameter changes enable the capacitor to maintain the required capacitance value even as overall device dimensions are reduced according to shrinking design rules.
3Quantity of substance
If vertically-oriented capacitor is used, then capacitance can be maintained, but misalignment risks increase
Solution Approach 1:
The patent employs preliminary action by forming the horizontally-oriented capacitor structure between adjacent transistors during the same fabrication process sequence. The capacitor dielectric layer is deposited and patterned in conjunction with the transistor formation steps, ensuring proper alignment is established early in the manufacturing process before subsequent steps that could introduce misalignment.
Data Source
AI summary
A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode, and the insulating layer extends above a top-most surface of the substrate.