Semiconductor Structure With Horizontal Capacitors and GAA Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As DRAM technology advances with smaller process nodes, the increasing aspect ratio of capacitors and the complexity of manufacturing lead to stability issues and higher costs.
Innovation Solution
A method for forming a semiconductor structure that includes dividing a substrate into areas for forming capacitor and gate-all-around structures, with the capacitor structures extending horizontally to improve stability and the gate-all-around structures having a wide channel area to reduce short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor structures are formed vertically to increase integration density, then storage capacity is improved, but structural stability deteriorates due to high aspect ratio
Solution Approach 1:
The patent transitions from vertical capacitor structures (high aspect ratio) to horizontal capacitor structures (low aspect ratio) by changing the orientation dimension. This dimensional change allows the capacitor to extend in the lateral direction rather than vertically, improving structural stability while maintaining integration density through stacked configurations.
Solution Approach 2:
The patent inverts the conventional vertical capacitor orientation by forming capacitors horizontally. This inversion of the structural orientation resolves the stability issue caused by high aspect ratios while achieving comparable or improved integration through alternative spatial arrangements.
2Volume of moving object
If process nodes are scaled down to reduce device size, then integration degree is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor structure into distinct functional regions: a first area for capacitor structures and a second area for gate-all-around structures. This segmentation allows independent optimization of each component's manufacturing process, simplifying overall fabrication while enabling continued scaling.
Solution Approach 2:
The patent applies different structural configurations to different regions: horizontal capacitor structures in the first area and gate-all-around structures in the second area. This local differentiation optimizes each region for its specific function while managing manufacturing complexity through region-specific process optimization.
3Area of moving object
If transistor size is reduced to increase integration, then device density is improved, but gate control capability deteriorates due to short channel effects
Solution Approach 1:
The patent employs gate-all-around structures that wrap around the channel in multiple dimensions, providing enhanced gate control from all directions. This multi-dimensional gating approach compensates for the reduced channel length, maintaining effective gate control even as transistor size decreases for higher integration.
Data Source
Figure 1~2a
Figure 2b~2d
Figure 2e~2g
AI summary
Embodiments of the disclosure provide a semiconductor structure and a method for forming a semiconductor structure. The method includes: providing a substrate, the substrate including a first isolation groove extending in a first direction and a plurality of active columns arranged in an array along the first direction and a third direction, the substrate being divided into a first area and a second area by the first isolation groove along a second direction, the active columns being supported through support structures, the first direction, the second direction and the third direction being perpendicular to each other in pairs, the first direction and the second direction being parallel to an upper surface of the substrate; forming semi-capacitor structures located in the first area and gate-all-around structures located in the second area in gaps between the active columns; processing the active columns and the semi-capacitor structures in the first area to form capacitor structures extending in the second direction; and forming first connecting structures connecting the gate-all-around structures and the capacitor structures in the first isolation groove.